Bert E Forbes

US Patent:

43153100, Feb 9, 1982

Filed:

Sep 28, 1979

Appl. No.:

6/079991

Inventors:

John A. Bayliss - Portland OR
George W. Cox - Portland OR
Bert E. Forbes - San Luis Obispo CA
Kevin C. Kahn - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 300
G06F 1516

US Classification:

364200

Abstract:

An input/output processor architecture for providing an interface between peripheral subsystems and a generalized data processor. The interface processor enables data to be transferred between two address spaces (the generalized data processor address space and an external processor I/O address space) by mapping a portion of the I/O address space into a portion of the GDP address space. This mapping facility provides the peripheral subsystem with a "window" into the associated GDP subsystem. It accepts addresses within a certain subrange, or subranges, and translates them into references into one or more GDP data segments. A function-request facility provides a functional capability over certain objects within the GDP address space. The two facilities provide software on an external processor with a window into the address space of the GDP that enables the software, via the function request means, to send messages to and receive messages from the GDP and to manipulate an environment provided for the external processor within its address space.