Bethann Lawrence

US Patent:

20150348870, Dec 3, 2015

Filed:

May 28, 2014

Appl. No.:

14/288852

Inventors:

- Armonk NY, US
BethAnn Lawrence - Essex Junction VT, US
Yun Shi - South Burlington VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 23/48
H01L 27/12
H01L 29/06
H01L 21/768
H01L 21/762

Abstract:

A method of forming a semiconductor structure in a semiconductor-on-insulator (SOI) substrate and semiconductor structure so formed are provided. The SOI substrate includes a semiconductor layer; a bulk semiconductor region underlying the semiconductor layer; and an insulation layer between the two. The method includes substantially simultaneously forming a first opening and a second opening extending from the semiconductor layer to the conductive region; introducing an insulating material to the side walls of the first opening; at least partially filling the first opening with a semiconductor material to provide an ohmic contact trench; and at least partially filling the second opening with an insulating material to form a device isolation trench. Insulating regions, for example, shallow trench isolation (STI) regions, may be formed about the device isolation trench and the ohmic contact trench. Semiconductor structures are also provided. The benefits of combining the features of SOI and STI structures are provided.

US Patent:

20140209908, Jul 31, 2014

Filed:

Apr 1, 2014

Appl. No.:

14/242203

Inventors:

- Armonk NY, US
James S. Dunn - Jericho VT, US
Dale W. Martin - Hyde Park VT, US
Charles S. Musante - South Burlington VT, US
BethAnn Rainey Lawrence - Williston VT, US
Leathen Shi - Yorktown Heights NY, US
Edmund J. Sprogis - Williston VT, US
Cornelia K. Tsang - Mohegan Lake NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 23/482
H01L 21/66

US Classification:

257 48, 257777

Abstract:

Methods for bonding substrate surfaces, bonded substrate assemblies, and design structures for a bonded substrate assembly. Device structures of a product chip are formed using a first surface of a device substrate. A wiring layer of an interconnect structure for the device structures is formed on the product chip. The wiring layer is planarized. A temporary handle wafer is removably bonded to the planarized wiring layer. In response to removably bonding the temporary handle wafer to the planarized first wiring layer, a second surface of the device substrate, which is opposite to the first surface, is bonded to a final handle substrate. The temporary handle wafer is then removed from the assembly.