Jan 2010 to Present IP Design and Verification InternArasan Chip Systems
Jun 2010 to Dec 2010 IP Design and Verification InternTata Consultancy Services, India Gurgaon, Haryana Nov 2007 to Jun 2009 System Assistants Engineer
Education:
San Jose State University Sep 2009 to Mar 2011 M.S in Electrical EngineeringUttar Pradesh Technical University Uttar Pradesh, INDIA Jan 2003 to Jan 2007 B.S in Electronics and Communication
Skills:
HDL'S: SystemVerilog Verilog VHDL SystemC Digital Design Tools: Modelsim Synopsys VCS Design Analyzer Design Vision Altera's Quartus II IC design tools: Cadence (Virtuoso Layout and Schematic Editors) Cadence NC-Verilog Languages: C C++ Perl Matlab Java PL/SQL J2ME Software Tools: Net Beans IDE MySQL Sun Java Wireless Toolkit 2.5 Beta Tomcat 5.5 Server