A ring oscillator circuit, such as a VCO, with a relatively high level of noise rejection for noise originating from both the voltage supply and ground. The ring oscillator circuit is composed of a plurality of differential delay circuits, each differential delay circuit generating a differential output signal that is a delayed (and preferably inverted) version of a differential input signal. Each differential delay circuit includes first and second input transistors for receiving the differential input signal. Each differential delay circuit also includes first and second load transistors coupled in parallel with the respective first and second input transistors. Each differential delay circuit further includes a first current source coupled between the first input transistor and a first power supply terminal (e. g. , a voltage supply terminal), a second current source coupled between the second input transistor and the first power supply terminal and a third current source coupled between the first and second input transistors and a second power supply terminal (e. g. , a ground terminal).
In a communications receiver for quadrature demodulation, a feedback technique for reducing the image response of the receiver. The communications receiver includes an I demodulator and a Q demodulator. A local oscillator (LO) signal is provided by a PLL to a quadrature LO generator that provides an LO_I signal to an I demodulator and an LO_Q signal to a Q demodulator. The LO_I and LO_Q signals are amplitude and phase-controlled versions of the LO signal. An image/signal ratio (I/S) detector detects the relative phase difference and the relative amplitude difference between the respective output terminals of the I demodulator and the Q demodulator and applies an amplitude control signal and a phase control signal to corresponding amplitude control and phase control inputs of the quadrature LO generator. The I/S detector calibrates the quadrature LO generator during the interstitial interval between the reception of data packets. The control signals from the I/S detector adjust the relative amplitude and phase of the LO_I and LO_Q signals in a manner that reduces the image response of the communications receiver.
High Noise Rejection Voltage-Controlled Ring Oscillator Architecture
A ring oscillator circuit, such as a VCO, with a relatively high level of noise rejection for noise originating from both the voltage supply and ground. The ring oscillator circuit is composed of a plurality of differential delay circuits, each differential delay circuit generating a differential output signal that is a delayed (and preferably inverted) version of a differential input signal. Each differential delay circuit includes first and second input transistors for receiving the differential input signal. Each differential delay circuit also includes first and second load transistors coupled in parallel with the respective first and second input transistors. Each differential delay circuit further includes a first current source coupled between the first input transistor and a first power supply terminal (e. g. , a voltage supply terminal), a second current source coupled between the second input transistor and the first power supply terminal and a third current source coupled between the first and second input transistors and a second power supply terminal (e. g. , a ground terminal).
Receiver Architecture Employing Low Intermediate Frequency And Complex Filtering
A communications receiver architecture characterized by a relatively low intermediate frequency (IF) and a polyphase filter. The receiver includes an input amplifier coupled to a carrier signal. Respective I and Q demodulators are coupled to the output of the input amplifier. A quadrature local oscillator (LO) generator provides respective LO_I and LO_Q inputs to the I demodulator and LO_Q inputs to the I demodulator and to the Q demodulator. The quadrature LO generator is driven by a phase-locked LO, and the LO frequency is such that an IF of, in one embodiment, approximately 1 MHz results. The I demodulator and Q demodulator outputs are applied through respective A/D converters to a polyphase filter. The polyphase filter outputs are then processed by a digital I/Q demodulator. Although a low IF is not generally understood to promote the image rejection performance of a receiver, substantial image rejection is afforded by the polyphase filter, thereby enabling the receiver to be realized almost entirely as a monolithic integrated semiconductor device.
High Noise Rejection Voltage-Controlled Ring Oscillator Architecture
A ring oscillator circuit, such as a VCO, with a relatively high level of noise rejection for noise originating from both the voltage supply and ground. The ring oscillator circuit is composed of a plurality of differential delay circuits, each differential delay circuit generating a differential output signal that is a delayed (and preferably inverted) version of a differential input signal. âEach differential delay circuit includes first and second input transistors for receiving the differential input signal. Each differential delay circuit also includes first and second load transistors coupled in parallel with the respective first and second input transistors. Each differential delay circuit further includes a first current source coupled between the first input transistor and a first power supply terminal (e. g. , a voltage supply terminal), a second current source coupled between the second input transistor and the first power supply terminal and a third current source coupled between the first and second input transistors and a second power supply terminal (e. g. , a ground terminal).
High Noise Rejection Voltage-Controlled Ring Oscillator Architecture
A ring oscillator circuit, such as a VCO, with a relatively high level of noise rejection for noise originating from both the voltage supply and ground. The ring oscillator circuit is composed of a plurality of differential delay circuits, each differential delay circuit generating a differential output signal that is a delayed (and preferably inverted) version of a differential input signal. ‘Each differential delay circuit includes first and second input transistors for receiving the differential input signal. Each differential delay circuit also includes first and second load transistors coupled in parallel with the respective first and second input transistors. Each differential delay circuit further includes a first current source coupled between the first input transistor and a first power supply terminal (e. g. , a voltage supply terminal), a second current source coupled between the second input transistor and the first power supply terminal and a third current source coupled between the first and second input transistors and a second power supply terminal (e. g. , a ground terminal).
Enhanced Interleave Type Error Correction Method And Apparatus
Bin Liu - Newark CA, US Edmun ChianSong Seng - Singapore, SG UttHeng Kan - Singapore, SG
Assignee:
Seagate Technology LLC - Scotts Valley CA
International Classification:
G11C029/00
US Classification:
714765
Abstract:
An enhanced interleave type error correction method is provided in which decoding of an enhanced interleave block is done. Subsequently the decoding may be done by decoding the estimated codewords multiple times using a single error correction code. In addition, a decoder and a digital communication system for implementing the enhanced interleave type error correction method are provided.
In a communications receiver for quadrature demodulation, a feedback technique for reducing the image response of the receiver. The communications receiver includes an I demodulator and a Q demodulator. A local oscillator (LO) signal is provided by a PLL to a quadrature LO generator that provides an LO_I signal to an I demodulator and an LO_Q signal to a Q demodulator. The LO_I and LO_Q signals are amplitude and phase-controlled versions of the LO signal. An image/signal ratio (I/S) detector detects the relative phase difference and the relative amplitude difference between the respective output terminals of the I demodulator and the Q demodulator and applies an amplitude control signal and a phase control signal to corresponding amplitude control and phase control inputs of the quadrature LO generator. The I/S detector calibrates the quadrature LO generator during the interstitial interval between the reception of data packets. The control signals from the I/S detector adjust the relative amplitude and phase of the LO_I and LO_Q signals in a manner that reduces the image response of the communications receiver.
Broadcom Corporation Irvine, CA Jun 2012 to Sep 2014 Principal Systems EngineerMTI Laboratory Inc El Segundo, CA Aug 2010 to May 2012 Senior Systems EngineerAlcon Laboratories Inc Irvine, CA Aug 2009 to Jul 2010 Senior Systems Design EngineerSkyworks Solutions Inc Irvine, CA Sep 2004 to Jul 2009 Principal Systems EngineerZigTeck, Inc
Dec 2003 to Aug 2004 Sr. Hardware Systems Design EngineerBaySpec Inc Fremont, CA Jul 2002 to Nov 2003 Sr. Electronics Design EngineerSorrento Networks San Diego, CA Mar 2001 to May 2002 Sr. Staff Hardware EngineerPairGain/ADC Telecommunications Tustin, CA Mar 2000 to Mar 2001 Sr. Hardware Design EngineerSR Telecom Inc Kanata, ON Feb 1998 to Mar 2000 Sr. Hardware EngineerWoodward Dr Ottawa, ON Jan 1995 to Jan 1998 Telecommunications Systems Engineer
Education:
University of New Brunswick Fredericton, NB 1991 M.Sc. in Electrical EngineeringXi'an University of Science and Technology 1982 B.Sc. in Electrical Engineering
Jul 2010 to 2000 Program Manager, Supply Chain Network Design & ManagementCISCO SYSTEMS San Jose, CA Jun 2008 to Jul 2010 Program Manager, Supply Chain Planning and OperationCISCO SYSTEMS San Jose, CA Jul 2007 to May 2008 Project Manager, WW Reverse Logistics & Distribution Channel Return OperationsTELUS MOBILITY Toronto, ON May 2003 to Jan 2007 Senior Business Analyst, Engineering GroupBeissbarth GmbH
May 1994 to Jun 1999 National Operations Manager
Education:
MASSACHUSETTS INSTITUTE OF TECHNOLOGY Cambridge, MA 2007 M.E., Supply Chain Management in Supply Chain design and StrategyGeorge Mason University Fairfax, VA 2001 M.S. in Operations Research and Management ScienceBEIJING INSTITUTE OF TECHNOLOGY 1992 BEng in Mechanical Engineering
Skills:
Program Management, Demand & Planning, Inventory management, Predictive Data Analytics, Data visualization, Supply Chain Resiliency, Supply chain taxes and duty, Chinese
Jan 2013 to 2000 Research ScientistQuantum Global Technologies, LLC Fremont, CA May 2011 to Dec 2012 Lab Reporting Analyst IIApplied Materials Fremont, CA Dec 2005 to May 2011 Lab Reporting Analyst I
Education:
University of California at Berkeley Berkeley, CA 2001 to 2005 Bachelor in Applied MathematicsUC Berkeley
Googleplus
Bin Liu
Work:
NEET
Education:
University of Bristol - Advanced computing: Internet technologies with Security
Bin Liu
Bin Liu
Lived:
San Francisco, CA
About:
Trail runner and mountain hiker.
Bin Liu
Bin Liu
About:
My name in Chinese is 赵斌,I was born in 1980s. I graduated from University of Electronic Science and Technology of China (UESTC). In spare time, I like reading book, surfing internet, watching movie an...
Bin Liu
About:
Nothing to show!
Bin Liu
Bin Liu
About:
Hello, I am Bin Liu from U of Michigan, now working at NEC Labs in Cupertino, CA.
Reference: Conferring liver selectivity to a thyromimetic using a novel nanoparticle increases therapeutic efficacy in a diet-induced obesity animal model by Ruiling Wu, Theeraphop Prachyathipsakul, Jiaming Zhuang, Hongxu Liu, Yanhui Han, Bin Liu, Shuai Gong, Jingyi Qiu, Siu Wong, Alexander Ribbe,
Date: Nov 06, 2023
Category: Technology
Source: Google
What Lies Below the Moon's Crust? China's Yutu-2 Rover May Be the First to Find Out.
"Very large impact craters for example, the South Pole-Aitken Basin can potentially penetrate through the crust and sample the lunar mantle," study co-author Bin Liu, a planetary scientist at the Key Laboratory of Lunar and Deep Space Exploration in Beijing, told Space.com.
Date: May 15, 2019
Category: Science
Source: Google
ZTE Dives After Agreeing to $1 Billion Fine and Major Revamp
ZTE should have a significant loss in FY18E due to the penalty in addition to near-term operational challenges due to management change and increased overseas growth uncertainties, Citi analyst Bin Liu wrote.