Binglong L Zhang

US Patent:

6601123, Jul 29, 2003

Filed:

Dec 23, 1999

Appl. No.:

09/471797

Inventors:

Binglong Zhang - Portland OR
Roland Pang - Phoenix AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1700

US Classification:

710305, 326 86

Abstract:

A differential bus having a controllable differential signal development rate. A differential signal development rate control circuit is provided to control the development rate of a differential signal on a differential bus.

US Patent:

6687844, Feb 3, 2004

Filed:

Sep 28, 2000

Appl. No.:

09/671314

Inventors:

Binglong Zhang - Austin TX

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 104

US Classification:

713503, 713500, 713501

Abstract:

A device and method to detect and correct clock duty cycle skew detected in high performance microprocessor having a very high frequency clock. The device relies on a delay chain circuit to delay the clock signal and determine the presence of clock duty cycle skew. The device uses simple latches, flops and phase-detectors to compare and identify the nature of the clock duty cycle skew. Simple logic is then employed to measure and determine the amount and direction of de-skew to apply to the clock signal. After the de-skew operation, the clock duty cycle cycles used to control the execution of the microprocessor are of uniform time duration.

US Patent:

6703672, Mar 9, 2004

Filed:

Aug 25, 1997

Appl. No.:

08/917796

Inventors:

Lawrence N. Brigham - Beaverton OR
Chia-Hong Jan - Portland OR
Binglong Zhang - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 2976

US Classification:

257407, 257412, 257413

Abstract:

A polysilicon/amorphous silicon composite layer for improved linewidth control in the patterning of gate electrodes, in the manufacture of metal oxide semiconductor (MOS) devices. The formation of a composite polysilicon/amorphous silicon gate in an integrated circuit gives the device the electrical performance and doping qualities of a polysilicon gate and also gives the device the smoothness of an amorphous silicon gate which improves line definition during gate patterning.

US Patent:

7260736, Aug 21, 2007

Filed:

Nov 19, 2003

Appl. No.:

10/718282

Inventors:

Binglong Zhang - Austin TX, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 11/00

US Classification:

713503, 713500

Abstract:

A device and method to detect and correct for clock duty cycle skew in a high performance microprocessor having a very high frequency clock. The device includes a delay chain circuit to delay the clock signal and to determine the presence of clock duty cycle skew. The device uses simple latches, flops, and phase-detectors to compare and identify the nature of the clock duty cycle skew. Simple logic is employed to measure and determine the amount and direction of de-skew to apply to the clock signal. After the de-skew operation, the clock duty cycle cycles used to control the execution of the microprocessor are of a more uniform time duration.

US Patent:

60178191, Jan 25, 2000

Filed:

Nov 14, 1997

Appl. No.:

8/970715

Inventors:

Lawrence N. Brigham - Beaverton OR
Chia-Hong Jan - Portland OR
Binglong Zhang - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 213213
H01L 21324
H01L 21441

US Classification:

438657

Abstract:

A polysilicon/amorphous silicon composite layer for improved linewidth control in the patterning of gate electrodes, in the manufacture of metal oxide semiconductor (MOS) devices. The formation of a composite polysilicon/amorphous silicon gate in an integrated circuit gives the device the electrical performance and doping qualities of a polysilicon gate and also gives the device the smoothness of an amorphous silicon gate which improves line definition during gate patterning.

US Patent:

20200081713, Mar 12, 2020

Filed:

Sep 6, 2018

Appl. No.:

16/123608

Inventors:

- Armonk NY, US
Sam G. Chu - Round Rock TX, US
Dung Q. Nguyen - Austin TX, US
Binglong Zhang - Austin TX, US
Howard Levy - Austin TX, US
David R. Terry - Austin TX, US
Steven J. Battle - Austin TX, US

International Classification:

G06F 9/30
G06F 12/02

Abstract:

An approach is provided in which a system writes a set of data into a register file entry that includes a first memory array and a second memory array. The register file entry also includes a set of first write ports corresponding to the first memory array and a set of second write ports corresponding to the second memory array. The system configures a selection bit based on determining that a selected one of the set of first write ports is utilized to store the set of data in the first memory array. In turn, the system reads the set of data out of the first memory array based on the configured selection bit.