Binh Van Le

US Patent:

6881593, Apr 19, 2005

Filed:

May 31, 2002

Appl. No.:

10/159682

Inventors:

Binh Q. Le - Vienna VA, US
Ark L. Lew - Ellicott City MD, US
Paul D. Schwartz - Arnold MD, US
Seppo J. Lehtonen - Columbia MD, US
Sharon X. Ling - Clarksville MD, US

Assignee:

The Johns Hopkins University - Baltimore MD

International Classification:

H01L021/66

US Classification:

438 14, 438 15, 438 18, 257 48, 257777, 257778, 257782, 257784

Abstract:

A semiconductor die adapter assembly includes a semiconductor die cut from a wafer, the die having an active surface including bond pads. A die adapter, also having bond pads, is bonded to the semiconductor die. Die-to-adapter connectors electrically connect the die bond pads to the adapter bond pads. Finally, adapter-to-substrate connectors electrically connect the adapter bond pads to a device substrate. Having bond pads on the die adapter eliminates the need to break and remake the electrical connections to the original bond pads on the die during burn-in testing of the die.

US Patent:

62952285, Sep 25, 2001

Filed:

Feb 28, 2000

Appl. No.:

9/514933

Inventors:

Joseph G. Pawletko - Germantown MD
Binh Quang Le - Mountain View CA
James M. Hong - Los Angeles CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 1606

US Classification:

36518522

Abstract:

A programming control circuit programs a memory cell in accordance to a programming signal value that can be varied by a test equipment. The programming control circuit comprises a signal storage device, a signal output circuit, and a verification circuit. The signal storage device stores the programming signal value. The test equipment can be coupled to the signal storage device to write the programming signal value into the signal storage device. The signal output circuit is coupled to the signal storage device to receive the programming signal value. The signal output circuit converts the programming signal value into a programming signal and outputs the programming signal to the memory cell. The verification circuit determines whether the memory cell is successfully programmed. If the memory cell is not successfully programmed, the programming control circuit increases the programming signal value.

US Patent:

62557998, Jul 3, 2001

Filed:

Dec 29, 1999

Appl. No.:

9/474515

Inventors:

Binh Q. Le - Vienna VA
Ark L. Lew - Ellicott City MD
Paul D. Schwartz - Arnold MD
Albert C. Sadilek - Elkridge MD
Joseph J. Suter - Ellicott City MD
Jason E. Jenkins - Columbia MD
Sharon X. Ling - Clarksville MD

Assignee:

The Johns Hopkins University - Baltimore MD

International Classification:

H02J 700
H02K 500
A43B 702

US Classification:

320107

Abstract:

The invention comprises a means for generating energy while walking or running for storage in a rechargeable battery. One embodiment uses lever arm movement in the heel of a shoe resulting from normal walking or running to generate energy from a built-in generator. The linear or rotational motion of the lever arm engages the circular gear assembly and turns the generator/motor/turbine, thus generating power. The second embodiment uses fluid reservoirs embedded in the shoes. Pressure changes resulting from normal walking or running moves the fluid through a narrow channel connecting two reservoirs, thus generating power by rotating a flywheel and an attached motor/generator/turbine in the middle of the channel. Secondary (rechargeable) batteries are incorporated into the invention either in an integrated form or as an add-on design. Additional features include a digital diagnostic data output, which would serves as a "fuel gauge" for the secondary batteries, and a smart charging circuit that efficiently controls battery charging from a generator output that varies with step rate and force.

US Patent:

63044870, Oct 16, 2001

Filed:

Feb 28, 2000

Appl. No.:

9/514404

Inventors:

Joseph G. Pawletko - Germantown MD
Binh Quang Le - Mountain View CA
James M. Hong - Los Angeles CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 1606

US Classification:

36518522

Abstract:

A voltage control circuit that programs or erases memory cells comprises an internal voltage value store, a register device selectively coupled to an external voltage value source or the internal voltage value store to receive a voltage value, a voltage output circuit coupled to the register device to receive the voltage value and to output a corresponding voltage to the memory cells, and a verify circuit determining the time to successfully program or erase the memory cells. The register device allows the memory cells to be programmed or erased with voltage values designated by the external voltage value source to determine programming and erasing characteristics of the memory cells. Voltage values producing acceptable programming and erasing characteristics are saved in the internal voltage value store.

US Patent:

62466119, Jun 12, 2001

Filed:

Feb 28, 2000

Appl. No.:

9/514560

Inventors:

Joseph G. Pawletko - Germantown MD
Binh Quang Le - Mountain View CA
James M. Hong - Los Angeles CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 1600

US Classification:

36518529

Abstract:

An erase control circuit erases a memory cell in accordance to an erase signal value that can be varied by a test equipment. The erase control circuit comprises a signal storage device, a signal output circuit, and a verification circuit. The signal storage device stores the erase signal value. A test equipment can be coupled to the signal storage device to write the programming signal value into the signal storage device. The signal output circuit is coupled to the signal storage device to receive the erase signal value. The signal output circuit converts the erase signal value into an erase signal and outputs the erase signal to the memory cell. The verification circuit determines whether the memory cell is successfully erased. If the memory cell is not successfully erased, the erase control circuit increases the erase signal value.