Joseph G. Pawletko - Germantown MD Binh Quang Le - Mountain View CA James M. Hong - Los Angeles CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G11C 1606
US Classification:
36518522
Abstract:
A programming control circuit programs a memory cell in accordance to a programming signal value that can be varied by a test equipment. The programming control circuit comprises a signal storage device, a signal output circuit, and a verification circuit. The signal storage device stores the programming signal value. The test equipment can be coupled to the signal storage device to write the programming signal value into the signal storage device. The signal output circuit is coupled to the signal storage device to receive the programming signal value. The signal output circuit converts the programming signal value into a programming signal and outputs the programming signal to the memory cell. The verification circuit determines whether the memory cell is successfully programmed. If the memory cell is not successfully programmed, the programming control circuit increases the programming signal value.
Register Driven Means To Control Programming Voltages
Joseph G. Pawletko - Germantown MD Binh Quang Le - Mountain View CA James M. Hong - Los Angeles CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G11C 1606
US Classification:
36518522
Abstract:
A voltage control circuit that programs or erases memory cells comprises an internal voltage value store, a register device selectively coupled to an external voltage value source or the internal voltage value store to receive a voltage value, a voltage output circuit coupled to the register device to receive the voltage value and to output a corresponding voltage to the memory cells, and a verify circuit determining the time to successfully program or erase the memory cells. The register device allows the memory cells to be programmed or erased with voltage values designated by the external voltage value source to determine programming and erasing characteristics of the memory cells. Voltage values producing acceptable programming and erasing characteristics are saved in the internal voltage value store.
Topology For Individual Battery Cell Charge Control In A Rechargeable Battery Cell Array
Paul D. Schwartz - Thurmont MD Binh Q. Le - Vienna VA Ark L. Lew - Ellicott City MD Joseph J. Suter - Clarksville MD
Assignee:
The Johns Hopkins University - Baltimore MD
International Classification:
H02J 700
US Classification:
320122
Abstract:
A microprocessor-based charge control architecture which provides individual battery cell charge control in order to insure an equality of charge among all cells in a rechargeable battery cell array during a single charge cycle. The array is arranged in parallel strings with an identical number of cells in series in each string. The microprocessor controls the amount of charge current in each battery cell via a shunt element for each battery cell, and adjusts the shunt element to bypass a portion of the string current for each battery cell. The invention also permits charge control algorithms to be conveniently updated, provides individual cell coulometry, and autonomously monitors and corrects conditions which can result in battery failure. Any type of rechargeable battery cell and array size can be accommodated. The array size can be set to accommodate the specific voltage and load current requirements of each application.
Joseph G. Pawletko - Germantown MD Binh Quang Le - Mountain View CA James M. Hong - Los Angeles CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G11C 1600
US Classification:
36518529
Abstract:
An erase control circuit erases a memory cell in accordance to an erase signal value that can be varied by a test equipment. The erase control circuit comprises a signal storage device, a signal output circuit, and a verification circuit. The signal storage device stores the erase signal value. A test equipment can be coupled to the signal storage device to write the programming signal value into the signal storage device. The signal output circuit is coupled to the signal storage device to receive the erase signal value. The signal output circuit converts the erase signal value into an erase signal and outputs the erase signal to the memory cell. The verification circuit determines whether the memory cell is successfully erased. If the memory cell is not successfully erased, the erase control circuit increases the erase signal value.
The present invention is directed to impregnating a support material with a metal phthalocyanine oxidation catalyst dissolved in monoethanol amine. More specifically, the invention is directed to the method of impregnating a catalyst support such as carbon particles with an aqueous solution of monoethanol amine wherein the monoethanol amine solvent is present in an amount from about 0. 25% to about 50% by weight.
Treatment Of Mercaptan-Containing Streams Utilizing Nitrogen Based Promoters
Binh N. Le - Humble TX Gilbert D. Veasey - Dickinson TX
Assignee:
Merichem Company - Houston TX
International Classification:
C10G 2900
US Classification:
208207
Abstract:
An improved method of treating streams having mercaptan or mercaptan-based compounds therein particularly adapted for the processes of sweetening sour hydrocarbons and regenerating spent caustic solutions is described. The invention comprises contacting a first stream having the mercaptan or mercaptan-based compounds therein with a second stream in the presence of effective amounts of a nitrogen-based promoter to promote the extraction and/or the catalytic oxidation of the mercaptan compounds therein. The invention herein disclosed and described is applicable in a wide variety of apparatus and processes adapted for sweetening and regeneration operations.
Dr. Le graduated from the Med & Pharm Univ, Ho Chi Minh City, Viet Nam (840 01 Prior 1/71) in 1974. He works in Modesto, CA and specializes in Family Medicine.
Nov 2012 to 2000 Technical SupportJabez Transitional Center of Dr. Sheri Bond
2006 to 2000 Independent IT Consultant / AdviserCQLSoft LLC Manassas, VA 1999 to 2002 Software AnalystDecisions Support Systems Reston, VA 1997 to 1999 LAN Admin
Education:
University of Wisconsin-Milwaukee Milwaukee, WI Jun 2012 B.S. in Science and Technology
2008 to 2000 Site Manager and Project ManagerDow Chemical Houston, TX 2006 to 2008 Senior Piping Designer/CheckerIntel Corporation Hillsboro, OR 2004 to 2006 Project ManagerFluor Corporation
2000 to 2004 Project EngineerC&E Corporation
1996 to 2000 Piping DesignerChevron Phillips Chemical Company LP
1994 to 1996 Piping Designer
Education:
Vietnam National University B.S. in Mechanical Engineering