Binh H Le

US Patent:

6370061, Apr 9, 2002

Filed:

Jun 19, 2001

Appl. No.:

09/884583

Inventors:

Santosh K. Yachareni - Santa Clara CA
Kazuhiro Kurihara - Sunnyvale CA
Binh Q. Le - San Jose CA
Michael S. C. Chung - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited - Kanagawa

International Classification:

G11C 1634

US Classification:

36518522, 36518503, 36518509, 3651852, 36518907, 36518909

Abstract:

The present invention relates to flash memory systems and methods to determine the threshold voltage of core cells. In one exemplary system, there is provided a method of characterizing the high end of the threshold voltage distribution of an array of programmed cells. In accordance with the invention, an exemplary system and method are presented to apply a varying characterization signal operably through a high breakdown voltage periphery donut transistor and wordline drive transistors, which are driven into saturation by a boosted gate voltage which is higher than the applied varying characterization signal, in a manner which provides for the accurate determination of the V of the core cells, through the comparison of the conduction in a reference cell to that of the conduction in a core cell produced by a varying characterization signal applied to the core cell gate.

US Patent:

6424570, Jul 23, 2002

Filed:

Jun 26, 2001

Appl. No.:

09/892189

Inventors:

Binh Q. Le - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 1604

US Classification:

36518518, 365226

Abstract:

A system is described for generating a charge pump voltage for flash memory operations, wherein a supply voltage detection circuit (e. g. , analog to digital converter, digital thermometer) is configured to detect a supply voltage value and generate one or more supply voltage level detection signals associated therewith. The system further includes a charge pump circuit comprising one or more stages operable to receive a supply voltage and generate the charge pump output voltage having a value greater than the supply voltage, and a charge pump compensation circuit operably coupled to the supply voltage detection circuit and the charge pump circuit. The charge pump compensation circuit is operable to receive the one or more output signals from the supply voltage detection circuit and modulate a capacitive loading associated with the charge pump circuit based on the one or more output signals, thereby creating an improved low power charge pump which uses a modulated pumping capacitance to compensate for fluctuations of the input power supply (for example, V ), to produce a slow ripple and low noise output which may be used as a pumped voltage for various mode operations (e. g. , erase, program modes) of memory cells.

US Patent:

6493266, Dec 10, 2002

Filed:

Apr 9, 2001

Appl. No.:

09/829193

Inventors:

Santosh K. Yachareni - Santa Clara CA
Darlene G. Hamilton - San Jose CA
Binh Q. Le - San Jose CA
Kazuhiro Kurihara - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited - Kanagawa

International Classification:

G11C 1134

US Classification:

36518522, 36518524

Abstract:

A method and system are disclosed for memory cell soft program and soft program verify, to adjust, or correct the threshold voltage between a target minimum and maximum, which may be employed in association with a dual bit memory cell architecture. The method includes applying one reference voltage signal to the over erased core cell, and a different reference voltage signal to the reference cell, comparing the two currents produced by each, selectively verifying proper soft programming of one or more bits of the cell, determining that the dual bit memory cell is properly soft programmed. The method may also comprise selectively re-verifying proper soft programming of the cells after selectively soft programming at least one or more bits of the cell.

US Patent:

6510082, Jan 21, 2003

Filed:

Oct 23, 2001

Appl. No.:

09/999869

Inventors:

Binh Q. Le - San Jose CA
Michael A. Van Buskirk - Saratoga CA
Santosh K. Yachareni - Santa Clara CA
Michael S. C. Chung - San Jose CA
Kazuhiro Kurihara - Sunnyvale CA
Shane Hollmer - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited - Kanagawa

International Classification:

G11C 1604

US Classification:

36518516, 36518521

Abstract:

A system is disclosed for producing an indication of the logical state of a flash memory cell for virtual ground flash memory operations. The system comprises a bit line charge and hold circuit which is operable to apply a read sense voltage (e. g. , about 1. 2 volts) to a bit line associated with the drain terminal of a cell of the flash array adjacent to the cell which is sensed, wherein the applied drain terminal voltage is substantially the same as the cell sense voltage (e. g. , about 1. 2 volts) applied to the drain terminal bit line of the selected memory cell to be sensed. The system further includes a selective bit line decode circuit which is operable to select the bit lines of a memory cell to be sensed and the bit line of an adjacent cell, and a core cell sensing circuit which is operable to sense a core cell sense current at a bit line associated with a drain terminal of the selected memory cell to be sensed during memory read operations, and produce an indication of the flash memory cell logical state, which is substantially independent of charge sharing leakage current to an adjacent cell.

US Patent:

6515903, Feb 4, 2003

Filed:

Jan 16, 2002

Appl. No.:

10/050254

Inventors:

Binh Q. Le - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 1604

US Classification:

36518518, 36518909, 365226, 327536

Abstract:

A system is disclosed for generating a regulated negative charge pump voltage for flash memory operations, wherein a capacitive voltage divider circuit comprising one or more MOS capacitors is configured to respond to the regulated output voltage of a negative charge pump circuit and an output circuit source loading and generate a voltage divider output signal associated therewith. The system also includes an initialization circuit which is configured to precharge the capacitors of the MOS capacitor voltage divider with a reference voltage. The system further includes a bias circuit operable to generate a bias voltage which is used in association with the MOS capacitors to insure they operate above a bias voltage which will maintain a minimum target capacitance within the voltage divider, resulting in a stable target regulation voltage. The negative regulator also includes an output circuit operable to source the negative charge pump output voltage to a supply voltage, and a negative regulator control circuit operably coupled to the initialization circuit and the capacitive voltage divider circuit, and operable to receive the bias circuit voltage and the associated MOS capacitor voltage divider circuit output, and operable to receive a negative charge pump output voltage and regulate an output circuit source loading via the supply voltage to produce a feedback to the negative charge pump circuit based on the target voltage value established by the MOS capacitor voltage divider, thereby creating a reduced area negative regulator used in conjunction with a negative charge pump circuit, which maintains a low power and simple regulator design, to produce a regulated charge pump output which may be used as a pumped voltage for various mode operations of memory cells.

US Patent:

6525966, Feb 25, 2003

Filed:

Dec 5, 2001

Appl. No.:

10/010985

Inventors:

Shane C. Hollmer - San Jose CA
Joseph G. Pawletko - New York NY
Binh Quang Le - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 1606

US Classification:

3651852, 36518521

Abstract:

Method and apparatus for a memory circuit having a sense amplifier circuit having a sensing amplifier connected to read the data content output of a memory cell where the sense amplifier circuit includes a current source transistor having a gate terminal and having a drain terminal connected to a voltage supply and having a source terminal connected to the sensing amplifier, with a selectable source current in order to account for variation from a desired source current due to variations in the designed source current transistor performance parameters.

US Patent:

6535424, Mar 18, 2003

Filed:

Jul 25, 2001

Appl. No.:

09/915018

Inventors:

Binh Q. Le - San Jose CA
Masaru Yano - Kodaira, JP
Santosh K. Yachareni - Santa Clara CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 1604

US Classification:

36518518, 36518523, 36518911

Abstract:

Flash memory array systems and methods are disclosed for producing a supply regulated boost voltage, wherein the application of a supply voltage to a supply voltage level detection circuit (e. g. , analog to digital converter, digital thermometer) which is used to generating one or more supply voltage level detection signals from measurement of the supply voltage level applied to the voltage boost circuit, which may be used as a boosted wordline voltage for the read mode operations of programmed memory cells, and wherein the supply voltage level detection signals are applied to a boosted voltage compensation circuit to generate one or more boosted voltage compensation signals which are applied to a voltage boost circuit operable to generate a regulated boosted voltage for a flash memory array of programmed core cells. Thus, a fast compensation means is disclosed for the V power supply variations typically reflected in the output of the boost voltage circuit supplied to the word line of the flash memory array, thereby generating wordline voltages during the read mode which are substantially independent of variations in the supply voltage.

US Patent:

6553493, Apr 22, 2003

Filed:

Apr 23, 1999

Appl. No.:

09/298688

Inventors:

Kenneth K. Okumura - Sunnyvale CA
Garret L. Simpson - San Jose CA
Jason N. Paul - San Jose CA
Binh P. Le - San Jose CA

Assignee:

VeriSign, Inc. - Mountain View CA

International Classification:

G06F 1130

US Classification:

713170, 713168, 713171, 713176, 713180

Abstract:

A method ( ) for assigning a key pair to an entity, such as a certification authority (CA ), includes the following steps. A key pair is generated ( ). It includes a private key and a public key which form a key pair for use in public-key cryptography. The key pair is stored ( ) in a cryptographic signing unit (CSU ). The CSU ( ) is then activated ( ). A request for a key pair is received ( ) from the entity ( ). Responsive to the request, the key pair is assigned ( ) to the entity ( ). In a preferred embodiment, an identifier ( ) is assigned to the key pair and preferably is different from identifiers assigned to other key pairs stored in the CSU ( ). The identifier ( ) is then included in a digital certificate ( ) issued to the entity ( ).