Binh Thi Pham

US Patent:

20220261351, Aug 18, 2022

Filed:

May 6, 2022

Appl. No.:

17/738919

Inventors:

- Santa Clara CA, US
Venkata Krishnan - Ashland MA, US
Andrew J. Herdrich - Hillsboro OR, US
Ren Wang - Portland OR, US
Robert G. Blankenship - Tacoma WA, US
Vedaraman Geetha - Fremont CA, US
Shrikant M. Shah - Chandler AZ, US
Marshall A. Millier - Banks OR, US
Raanan Sade - Haifa, IL
Binh Q. Pham - Hillsboro OR, US
Olivier Serres - Hudson MA, US
Christopher B. Wilkerson - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/0868
G06F 12/0897
G06F 3/06
G06F 12/0811
G06F 12/0871

Abstract:

Method and system for performing data movement operations is described herein. One embodiment of a method includes: storing data for a first memory address in a cache line of a memory of a first processing unit, the cache line associated with a coherency state indicating that the memory has sole ownership of the cache line; decoding an instruction for execution by a second processing unit, the instruction comprising a source data operand specifying the first memory address and a destination operand specifying a memory location in the second processing unit; and responsive to executing the decoded instruction, copying data from the cache line of the memory of the first processing unit as identified by the first memory address, to the memory location of the second processing unit, wherein responsive to the copy, the cache line is to remain in the memory and the coherency state is to remain unchanged.

US Patent:

20210405974, Dec 30, 2021

Filed:

Jun 27, 2020

Appl. No.:

16/914318

Inventors:

- Santa Clara CA, US
Robert Valentine - Kiryat Tivon, IL
Barukh Ziv - Haifa, IL
Amit Gradstein - Binyamina, IL
Simon Rubanovich - Haifa, IL
Zeev Sperber - Zichron Yackov, IL
Mark J. Charney - Lexington MA, US
Christopher J. Hughes - Santa Clara CA, US
Alexander F. Heinecke - San Jose CA, US
Evangelos Georganas - San Mateo CA, US
Binh Pham - Burlingame CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 7/78
G06F 17/16
G06F 9/30

Abstract:

Embodiments for a matrix transpose and multiply operation are disclosed. In an embodiment, a processor includes a decoder and execution circuitry. The decoder is to decode an instruction having a format including an opcode field to specify an opcode, a first destination operand field to specify a destination matrix location, a first source operand field to specify a first source matrix location, and a second source operand field to specify a second source matrix location. The execution circuitry is to, in response to the decoded instruction, transpose the first source matrix to generate a transposed first source matrix, perform a matrix multiplication using the transposed first source matrix and the second source matrix to generate a result, and store the result in a destination matrix location.

US Patent:

20210049102, Feb 18, 2021

Filed:

Mar 30, 2020

Appl. No.:

16/834845

Inventors:

- Santa Clara CA, US
Venkata Krishnan - Ashland MA, US
Andrew J. Herdrich - Hillsboro OR, US
Ren Wang - Portland OR, US
Robert G. Blankenship - Tacoma WA, US
Vedaraman Geetha - Fremont CA, US
Shrikant M. Shah - Chandler AZ, US
Marshall A. Millier - Banks OR, US
Raanan Sade - Haifa, IL
Binh Q. Pham - Hillsboro OR, US
Olivier Serres - Hudson MA, US
Christopher B. Wilkerson - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/0868
G06F 12/0897
G06F 3/06
G06F 12/0811
G06F 12/0871

Abstract:

Method and system for performing data movement operations is described herein. One embodiment of a method includes: storing data for a first memory address in a cache line of a memory of a first processing unit, the cache line associated with a coherency state indicating that the memory has sole ownership of the cache line; decoding an instruction for execution by a second processing unit, the instruction comprising a source data operand specifying the first memory address and a destination operand specifying a memory location in the second processing unit; and responsive to executing the decoded instruction, copying data from the cache line of the memory of the first processing unit as identified by the first memory address, to the memory location of the second processing unit, wherein responsive to the copy, the cache line is to remain in the memory and the coherency state is to remain unchanged.

US Patent:

20200233814, Jul 23, 2020

Filed:

Feb 10, 2020

Appl. No.:

16/786815

Inventors:

- Santa Clara CA, US
Mitchell DIAMOND - Shrewsbury MA, US
David KEPPEL - Mountain View CA, US
Samantika S. SURY - Westford MA, US
Binh PHAM - Burlingame CA, US
Shobha VISSAPRAGADA - Hudson MA, US

International Classification:

G06F 12/1027

Abstract:

Examples described herein relate to a computing system supporting custom page sized ranges for an application to map contiguous memory regions instead of many smaller sized pages. An application can request a custom range size. An operating system can allocate a contiguous physical memory region to a virtual address range by specifying a custom range sizes that are larger or smaller than the normal general page sizes. Virtual-to-physical address translation can occur using an address range circuitry and translation lookaside buffer in parallel. The address range circuitry can determine if a custom entry is available to use to identify a physical address translation for the virtual address. Physical address translation can be performed by transforming the virtual address in some examples.

US Patent:

20200104259, Apr 2, 2020

Filed:

Sep 28, 2018

Appl. No.:

16/147346

Inventors:

- Santa Clara CA, US
Lawrence C. Stewart - Wayland MA, US
Binh Pham - Hillsboro OR, US
Andrew Herdrich - Hillsboro OR, US
Venkata Krishnan - Ashland MA, US
Anil Vasudevan - Portland OR, US
Joseph Nuzman - Haifa, IL
Tsung-Yuan Tai - Portland OR, US

International Classification:

G06F 12/0862
G06F 12/0817
G06F 12/0842

Abstract:

A snapshot prefetcher to perform snapshot prefetching to improve performance of snapshot read operations. An apparatus embodiment includes a snapshot read tracking circuitry to track snapshot read requests made by a first processor core to read a plurality of cache lines, and to detect a snapshot read access stream based on the tracked snapshot read requests. A snapshot prefetch issuing circuitry of the apparatus to issue, based on the detected snapshot read access stream, one or more snapshot prefetch requests, including a first snapshot prefetch request to prefetch data from a first cache line stored in, and owned exclusively by, a first storage location outside the first processor core. The snapshot prefetch issuing circuitry further to store the prefetched data in a second storage location within the first processor core, wherein after the prefetch, exclusive ownership of the first cache line is to remain with the first storage location.

US Patent:

20190004958, Jan 3, 2019

Filed:

Jun 30, 2017

Appl. No.:

15/640060

Inventors:

- Santa Clara CA, US
Venkata Krishnan - Ashland MA, US
Andrew J. Herdrich - Hillsboro OR, US
Ren Wang - Portland OR, US
Robert G. Blankenship - Tacoma WA, US
Vedaraman Geetha - Fremont CA, US
Shrikant M. Shah - Chandler AZ, US
Marshall A. Millier - Banks OR, US
Raanan Sade - Haifa, IL
Binh Q. Pham - Hillsboro OR, US
Olivier Serres - Hudson MA, US
Christopher B. Wilkerson - Portland OR, US

International Classification:

G06F 12/0868
G06F 12/0811
G06F 3/06
G06F 12/0871

Abstract:

Method and system for performing data movement operations is described herein. One embodiment of a method includes: storing data for a first memory address in a cache line of a memory of a first processing unit, the cache line associated with a coherency state indicating that the memory has sole ownership of the cache line; decoding an instruction for execution by a second processing unit, the instruction comprising a source data operand specifying the first memory address and a destination operand specifying a memory location in the second processing unit; and responsive to executing the decoded instruction, copying data from the cache line of the memory of the first processing unit as identified by the first memory address, to the memory location of the second processing unit, wherein responsive to the copy, the cache line is to remain in the memory and the coherency state is to remain unchanged.