Bipin Rajendran

US Patent:

7567473, Jul 28, 2009

Filed:

Sep 18, 2007

Appl. No.:

11/857332

Inventors:

Matthew J. Breitwisch - Yorktown Heights NY, US
Chung H. Lam - Peekskill NY, US
Bipin Rajendran - White Plains NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 7/00

US Classification:

365203, 365204, 36518907

Abstract:

A method for operating a memory cell and memory array. The method of memory cell operation entails receiving a request to read a binary value stored in the memory cell. A pre-charging operation pre-charges a bit-line capacitor in an electronic circuit formed by the memory cell to a pre-charge voltage. A word-line in the electronic circuit is then activated. A discharging operation discharges the bit-line capacitor through the said memory cell in the electronic circuit to the word-line. Additionally, an electron discharge time measurement is started when the word-line is activated. The electron discharge time measurement is stopped when the voltage level in the bit-line falls below a pre-defined reference voltage. A determining operation determines the binary value from the measured electron discharge time.

US Patent:

7602631, Oct 13, 2009

Filed:

Sep 18, 2007

Appl. No.:

11/857356

Inventors:

Matthew J. Breitwisch - Yorktown Heights NY, US
Chung H. Lam - Peekskill NY, US
Bipin Rajendran - White Plains NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 11/00

US Classification:

365148, 365203, 365204

Abstract:

A memory array and computer program product for operating a memory cell and memory array. An embodiment of the invention entails receiving a binary value to be stored by a memory cell. A determining operation determines a target discharge time corresponding to the binary value. The target discharge time being the time needed to discharge a pre-charged circuit through the said memory cell to a predetermined level. A storing operation stores a characteristic parameter in the memory cell such that an electron discharge time through an electronic circuit formed, at least partially, by the memory cell, is substantially equal to the target discharge time.

US Patent:

7606067, Oct 20, 2009

Filed:

Jul 6, 2007

Appl. No.:

11/774539

Inventors:

Chung H. Lam - Peekskill NY, US
Bipin Rajendran - White Plains NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 16/04

US Classification:

36518503, 36518917

Abstract:

A method, system, and computer software product for operating a collection of memory cells. Each memory cell in the collection of memory cells is configured to store a binary multi-bit value delimited by characteristic parameter bands. In one embodiment, a transforming unit transforms an original collection of data to a transformed collection of data using a reversible mathematical operator. The original collection of data has binary multi-bit values arbitrarily distributed across the binary multi-bit values assigned to the characteristic parameter bands and the transformed collection of data has binary multi-bit values substantially uniformly distributed across the binary multi-bit values assigned to the characteristic parameter bands.

US Patent:

7639527, Dec 29, 2009

Filed:

Jan 7, 2008

Appl. No.:

11/970348

Inventors:

Ming-Hsiu Lee - Hsinchu, TW
Bipin Rajendran - White Plains NY, US
Chung Hon Lam - Peekskill NY, US

Assignee:

Macronix International Co., Ltd. - Hsinchu
International Business Machines Corporation - Armonk NY

International Classification:

G11C 11/00

US Classification:

365163, 365201

Abstract:

A method for testing an integrated circuit memory device includes applying a sequence of test pulses to a memory cell on the device, where the test pulses result in current through the memory cell having an amplitude dependent on the test pulse. Resistance in the memory cell is measured in response to the sequence of test pulses. A parameter set is extracted from the resistance measurements which includes at least one numerical coefficient that models dependency of the measured resistance on the amplitude of the current through the memory cell. The extracted numerical coefficient or coefficients are associated with the memory device, and used for controlling manufacturing operations.

US Patent:

7751217, Jul 6, 2010

Filed:

Jul 1, 2008

Appl. No.:

12/166311

Inventors:

Chung H. Lam - Peekskill NY, US
Brian L. Ji - Fishkill NY, US
Robert K. Montoye - Rocheter MN, US
Bipin Rajendran - White Plains NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 15/00

US Classification:

365 491, 365 4917, 365 4918, 365148, 365163

Abstract:

Content addressable memory device utilizing phase change devices. An aspect of the content addressable memory device is the use of a comparatively lower power search-line access element and a comparatively higher power word-line access element. The word-line access element is only utilized during write operations and the search-line access element is only utilized during search operations. The word-line access element being electrically coupled to a second end of a phase change memory element and a word-line. The search-line access element also being electrically coupled to the second end of the phase change memory element and a search-line. The search-line being electrically coupled to a match-line. A bit-line is electrically coupled to a first end of the phase change memory element. Additionally, a complementary set of access elements, a complementary phase change memory element, a complementary search-line, and a complementary bit-line are also included in the content addressable memory device.

US Patent:

7764533, Jul 27, 2010

Filed:

Sep 18, 2007

Appl. No.:

11/857321

Inventors:

Matthew J. Breitwisch - Yorktown Heights NY, US
Chung H. Lam - Peekskill NY, US
Bipin Rajendran - White Plains NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 11/00

US Classification:

365148, 365203, 365204

Abstract:

A memory array and computer program product for operating a memory cell and memory array. An embodiment of the invention entails receiving a request to read a binary value stored in the memory cell. A pre-charging operation pre-charges a bit-line capacitor in an electronic circuit formed by the memory cell to a pre-charge voltage. A word-line in the electronic circuit is then activated. A discharging operation discharges the bit-line capacitor through the said memory cell in the electronic circuit to the word-line. Additionally, an electron discharge time measurement is started when the word-line is activated. The electron discharge time measurement is stopped when the voltage level in the bit-line falls below a pre-defined reference voltage. A determining operation determines the binary value from the measured electron discharge time.

US Patent:

7782646, Aug 24, 2010

Filed:

Jun 30, 2008

Appl. No.:

12/165530

Inventors:

Chung Hon Lam - Peekskill NY, US
Bipin Rajendran - White Plains NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 15/00

US Classification:

365 4917, 365148, 365 491, 365163

Abstract:

A content addressable memory array storing stored words in memory elements. Each memory element stores one of at least two complementary binary bits as one of at least two complementary resistances. Each memory element is electrically coupled to an access device. An aspect of the content addressable memory array is the use of a biasing circuit to bias the access devices during a search operation. During the search operation, a search word containing a bit string is received. Each access device is biased to a complementary resistance value of a corresponding search bit in the search word. A match between the search word and stored word is indicated if the bits stored in the memory elements are complementary to the bits represented by the resistances in the access devices.

US Patent:

7811879, Oct 12, 2010

Filed:

May 16, 2008

Appl. No.:

12/121875

Inventors:

Chung Hon Lam - Peekskill NY, US
Bipin Rajendran - White Plains NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/8249

US Classification:

438234, 438202, 438625, 257 5, 257370, 257E27004, 257E2917

Abstract:

Techniques for forming a memory cell. An aspect of the invention includes forming FET gate stacks and sacrificial cell gate stacks over the substrate. Spacer layers are then formed around the FET gate stacks and around the sacrificial cell gate stacks. The sacrificial cell gate stacks are then removed such that the spacer layers around the sacrificial cell gate stacks are still intact. BJT cell stacks are then formed in the space between the spacer layers where the sacrificial cell gate stacks were formed and removed, the BJT cell stacks including an emitter layer. A phase change layer above the emitter contacts and an electrode above the phase change layer are then formed.