Biren A Shah

US Patent:

7120874, Oct 10, 2006

Filed:

Jun 18, 2002

Appl. No.:

10/174347

Inventors:

Biren Shah - Austin TX, US
Stephen Thorne - Austin TX, US
Matthew Novacek - Austin TX, US

Assignee:

National Instruments Corporation - Austin TX

International Classification:

G06F 15/00
G06F 13/00

US Classification:

715733, 709223, 715734, 715735

Abstract:

System and method for filtering attributes of a graphical program element (GPE) in a graphical program or diagram, e. g. , a property node, menu, property page, icon palette, etc. , based on targeted or configured resources. Input is received specifying or selecting a filter option from presented filter options. The filter options include 1) display all attributes of the GPE; 2) display attributes of the GPE associated with configured resources; and 3) display attributes of the GPE associated with selected configured resources. User input is received to access the GPE. Attributes for the GPE associated with the resources are retrieved from the database and displayed in accordance with the selected filtering option. The filtered attributes of the element are then selectable by a user for various operations, e. g. , to configure the graphical program, to configure resources, to initiate a purchase or order for the resources, and/or to install the resources, among others.

US Patent:

7574690, Aug 11, 2009

Filed:

Jul 16, 2004

Appl. No.:

10/892829

Inventors:

Biren Shah - Austin TX, US
Jacob Kornerup - Austin TX, US
Aljosa Vrancic - Austin TX, US
Jeffrey L. Kodosky - Austin TX, US
Michael L. Santori - Austin TX, US

Assignee:

National Instruments Corporation - Austin TX

International Classification:

G06F 9/44

US Classification:

717104, 700 83, 716 4, 715762, 710260

Abstract:

A system and method for creating a graphical program operable to execute a timed loop. A loop may be displayed in the graphical program and configured with timing information in response to user input. The timing information may include an execution period which specifies a desired period at which the loop should execute during execution of the graphical program. The timing information may also include information such as a timing source, offset, and priority. During execution of the graphical program, the execution period of the loop may control the rate at which the loop executes.

US Patent:

7703034, Apr 20, 2010

Filed:

Jul 16, 2004

Appl. No.:

10/892767

Inventors:

Jacob Kornerup - Austin TX, US
Biren Shah - Austin TX, US
Aljosa Vrancic - Austin TX, US
Bob Preis - Austin TX, US

Assignee:

National Instruments Corporation - Austin TX

International Classification:

G06F 3/048
G06F 3/00

US Classification:

715772, 715762, 715763

Abstract:

A system and method for viewing timing of one or more loops in a graphical program. A graphical program having one or more loops may be created. In one embodiment the one or more loops may include one or more timed loops, i. e. , the loops may be configured to execute according to particular execution periods. The graphical program may be executed, and timing analysis data regarding timing of the one or more loops during execution of the graphical program may be stored. A graphical user interface (GUI) for viewing timing of the one or more loops during execution of the graphical program may be displayed. In various embodiments the GUI may display any of various kinds of information regarding timing of the one or more loops, and any kind of visual presentation may be used in displaying the information.

US Patent:

7725874, May 25, 2010

Filed:

Aug 15, 2005

Appl. No.:

11/203816

Inventors:

Jacob Kornerup - Austin TX, US
Biren Shah - Austin TX, US
Aljosa Vrancic - Austin TX, US
Matthew Curtis - Austin TX, US
Steve Rogers - Austin TX, US

Assignee:

National Instruments Corporation - Austin TX

International Classification:

G06F 9/44

US Classification:

717105, 717113, 717114

Abstract:

A combination structure node is provided by a graphical programming development environment for use in a graphical program, where the combination structure node is operable to perform two or more control flow functions. For example, the combination structure node may be operable to perform two or more of: iteration, looping, conditional branching, sequencing, timed execution, event-driven execution, or other control flow functions. A user may include the combination structure node in a graphical program and associate a graphical code portion with the combination structure node. During execution of the graphical program, the combination structure node is operable to cause the associated graphical code portion to execute according to the two or more control flow functions performed by the combination structure node.

US Patent:

7761847, Jul 20, 2010

Filed:

Aug 15, 2005

Appl. No.:

11/204286

Inventors:

Jacob Kornerup - Austin TX, US
Biren Shah - Austin TX, US
Aljosa Vrancic - Austin TX, US

Assignee:

National Instruments Corporation - Austin TX

International Classification:

G06F 9/44
G06F 9/46

US Classification:

717113, 717104, 717105, 717109, 718100, 718102

Abstract:

A system and method for executing a plurality of graphical code portions as a timed sequence is described. The graphical code portions may be included in a graphical program and configured with information specifying a sequential order of execution and execution timing information. During execution of the graphical program, the graphical code portions are executed sequentially in the sequential order and in accordance with the execution timing information. In one embodiment a timed sequence structure node may be utilized to specify the timed sequence. For example, the user may include the timed sequence structure node in the graphical program and associate the plurality of graphical code portions with the timed sequence structure node such that the timed sequence structure node species a sequential order of execution for the graphical code portions. The user may also configure the timed sequence structure node with execution timing information for one or more of the graphical code portions.

US Patent:

7802229, Sep 21, 2010

Filed:

Aug 15, 2005

Appl. No.:

11/204369

Inventors:

Jacob Kornerup - Austin TX, US
Biren Shah - Austin TX, US
Aljosa Vrancic - Austin TX, US
Matthew Curtis - Austin TX, US
Steve Rogers - Austin TX, US

Assignee:

National Instruments Corporation - Austin TX

International Classification:

G06F 9/44

US Classification:

717109, 717106, 715763, 715771, 715804, 716 4, 716 11

Abstract:

A “timed loop with frames” node may be included in a graphical program. The “timed loop with frames” node may combine a timed loop with a timed sequence such that the timed sequence is executed at each iteration of the timed loop. The “timed loop with frames” node may be configured with first execution timing information that controls execution timing for the iterations of the loop. A plurality of graphical code portions may be included in the “timed loop with frames” such that a sequential order of execution for the graphical code portions is specified. The “timed loop with frames” node may be configured with second execution timing information that controls execution timing for the graphical code portions executed at each iteration.

US Patent:

8359567, Jan 22, 2013

Filed:

Apr 30, 2007

Appl. No.:

11/742528

Inventors:

Jacob Kornerup - Austin TX, US
Jeffrey L. Kodosky - Austin TX, US
Hugo A. Andrade - Austin TX, US
Biren Shah - Austin TX, US
Aljosa Vrancic - Austin TX, US
Michael L. Santori - Austin TX, US

Assignee:

National Instruments Corporation - Austin TX

International Classification:

G06F 9/44

US Classification:

717105, 717109

Abstract:

A system and method for specifying timing relationships among nodes in a graphical program. User input specifying desired timing of a first node with respect to timing of a second node may be received. In various embodiments, any kind of timing relationship or timing constraint between the first node and the second node may be specified. Timing information may be displayed on the display to visually indicate the timing of the first node with respect to timing of the second node. In one embodiment, displaying the timing information may comprise displaying a timing wire between the first node and the second node. The graphical program may be executed in such a way that the visually indicated timing of the first node with respect to timing of the second node is satisfied.

US Patent:

8397205, Mar 12, 2013

Filed:

Jul 16, 2004

Appl. No.:

10/893745

Inventors:

Jacob Kornerup - Austin TX, US
Jeffrey L. Kodosky - Austin TX, US
Hugo A. Andrade - Austin TX, US
Biren Shah - Austin TX, US
Aljosa Vrancic - Austin TX, US
Michael L. Santori - Austin TX, US

Assignee:

National Instruments Corporation - Austin TX

International Classification:

G06F 9/44
G06F 3/048

US Classification:

717100, 717105, 717113, 717121, 715771

Abstract:

A system and method for specifying timing relationships among nodes in a graphical program. User input specifying desired timing of a first node with respect to timing of a second node may be received. In various embodiments, any kind of timing relationship or timing constraint between the first node and the second node may be specified. Timing information may be displayed on the display to visually indicate the timing of the first node with respect to timing of the second node. In one embodiment, displaying the timing information may comprise displaying a timing wire between the first node and the second node. The graphical program may be executed in such a way that the visually indicated timing of the first node with respect to timing of the second node is satisfied.