Bradley A Taylor

US Patent:

7487212, Feb 3, 2009

Filed:

Dec 14, 2001

Appl. No.:

10/022325

Inventors:

Bradley Taylor - Menlo Park CA, US

Assignee:

Mirapoint Software, Inc. - Sunnyvale CA

International Classification:

G06F 13/00

US Classification:

709206

Abstract:

A method of providing a fast path message transfer agent is provided. The method includes receiving bytes of a message over a network connection and determining whether the number of bytes exceeds a predetermined threshold. If the number of bytes is less than a predetermined threshold, then the message is written only to memory. However, if the number of bytes exceeds the predetermined threshold, then some of the bytes (e. g. up to the predetermined threshold) are written to memory, wherein the remainder of the bytes are stored onto the non-volatile storage. If the message was received successfully by each destination, then the message is removed from the memory/non-volatile storage. If not, all failed destinations are identified and the message (with associated failed destinations) is stored on the nonvolatile storage for later sending.

US Patent:

7523434, Apr 21, 2009

Filed:

Sep 23, 2005

Appl. No.:

11/234490

Inventors:

Bradley L. Taylor - Santa Cruz CA, US
Arvind Sundararajan - Mountain View CA, US
Shay Ping Seng - San Jose CA, US
L. James Hwang - Menlo Park CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 17/50
H03K 17/693

US Classification:

716 16, 716 1, 716 17

Abstract:

An exemplary embodiment includes a method that receives a plurality of mathematical expressions having a plurality of input variables. The mathematical expressions can then be parsed, checked for proper syntax and one or more abstract syntax trees can be formed. Next, the input variables are then assigned to input ports of the dynamically configurable arithmetic unit. Then using the parsed mathematical expressions with the assigned input ports, a list of operations to be performed by the dynamically configurable arithmetic unit are determined. And lastly, an interface to the dynamically configurable arithmetic unit is generated using in part the variable-to-input port assignments and the list of operations.

US Patent:

7539953, May 26, 2009

Filed:

Dec 5, 2006

Appl. No.:

11/633977

Inventors:

Shay Ping Seng - San Jose CA, US
Jonathan B. Ballagh - Boulder CO, US
Roger B. Milne - Boulder CO, US
Bradley L. Taylor - Santa Cruz CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 1, 716 3, 716 17

Abstract:

Method, apparatus, and computer readable medium for circuit design is described. In one example, a model having at least one processor, at least one logic, and at least one shared memory is specified. The at least one shared memory is associated with the at least one processor. A memory map associated with the at least one shared memory and a bus adapter for coupling the memory map to the at least one processor are automatically generated.

US Patent:

7937259, May 3, 2011

Filed:

Dec 18, 2007

Appl. No.:

12/002838

Inventors:

Chi Bun Chan - San Jose CA, US
Bradley L. Taylor - San Jose CA, US
Nabeel Shirazi - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 9/455

US Classification:

703 28

Abstract:

Various embodiments of a co-simulation system are disclosed. In one embodiment, a data processing arrangement executes a simulator that simulates a first block of an electronic circuit design. A first clock source generates a first clock signal, and a second clock source generates a second clock signal. The first and second clock signals are independent one from another, and an operating frequency of the second clock signal is dynamically adjustable from a clock control interface. A programmable logic device (PLD) is configured with logic that includes a co-simulation interface clocked by the first clock signal, a second block of the electronic circuit design that is clocked by the second clock signal, and a synchronizer that controls data transmission between the co-simulation interface and the second block.

US Patent:

8010590, Aug 30, 2011

Filed:

Jul 19, 2007

Appl. No.:

11/880141

Inventors:

Bradley L. Taylor - Santa Cruz CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 7/38

US Classification:

708524, 708230

Abstract:

A configurable arithmetic block for implementing arithmetic functions in a device having programmable logic is described. The configurable arithmetic block comprises a first plurality of registers coupled to receive input data; a second plurality of registers coupled to receive input data; an arithmetic function circuit having a plurality of arithmetic function elements, each arithmetic function element coupled to at least one other arithmetic function element of the plurality of arithmetic function elements and coupled to receive outputs of at least one of the first plurality of input registers and the second plurality of input registers; and an output coupled to the arithmetic function circuit. A method of implementing a configurable arithmetic block in a device having programmable logic is also disclosed.

US Patent:

8024678, Sep 20, 2011

Filed:

Apr 1, 2009

Appl. No.:

12/416333

Inventors:

Bradley L. Taylor - Santa Cruz CA, US
Arvind Sundararajan - Sunnyvale CA, US
Shay Ping Seng - San Jose CA, US
L. James Hwang - Portola Valley CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716100, 716104, 716126, 716128, 708170, 708490, 708495, 712200, 712220, 712221, 712222, 712223

Abstract:

An interface to a dynamically configurable arithmetic unit can include data alignment modules, where each data alignment module receives input variables being associated with one or more arithmetic expressions. The interface can include multiplexers coupled to the data alignment modules, wherein a data alignment module has outputs coupled to a first multiplexer. The first multiplexer can have a selection line and an output coupled to an input port of the dynamically configurable arithmetic unit. The interface can include a second multiplexer having input instructions and the selection line, where each instruction is associated with one of the arithmetic expressions and has an operation to be performed by the dynamically configurable arithmetic unit. The second multiplexer is configurable to provide selected ones of the input instructions to the dynamically configurable arithmetic unit through an output of the second multiplexer responsive to the selection line.

US Patent:

8117247, Feb 14, 2012

Filed:

Jul 19, 2007

Appl. No.:

11/880140

Inventors:

Bradley L. Taylor - Santa Cruz CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 7/38

US Classification:

708235, 708524

Abstract:

A configurable arithmetic block in a device having programmable logic for implementing arithmetic functions is disclosed. The configurable arithmetic block comprises a plurality of input registers coupled to receive multiple bit words; an arithmetic function circuit coupled to receive the multiple bit words; an output selection circuit coupled to receive the output of the plurality of input registers and an output of the arithmetic function circuit; and a plurality of output registers coupled the output selection circuit. A method of implementing arithmetic functions in a device having programmable logic is also disclosed.

US Patent:

8539011, Sep 17, 2013

Filed:

Jul 19, 2007

Appl. No.:

11/880361

Inventors:

Bradley L. Taylor - Santa Cruz CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 7/38

US Classification:

708232, 708235

Abstract:

A device having programmable logic for implementing arithmetic functions is disclosed. The device comprises an input port coupled to receive a configuration bitstream; a plurality of configurable arithmetic blocks, each configurable arithmetic block comprising configurable circuits for implementing arithmetic functions according to bits of the configuration bitstream; a plurality of input registers coupled to receive multi-bit input words to be processed by the plurality of configurable arithmetic blocks; and an output register enabled to generate an output word. A method of implementing an arithmetic function in a device having programmable logic is also disclosed.