Bradley Jonathan Taylor

US Patent:

6347346, Feb 12, 2002

Filed:

Jun 30, 1999

Appl. No.:

09/343477

Inventors:

Bradley L. Taylor - Oakland CA

Assignee:

Chameleon Systems, Inc. - Sunnyvale CA

International Classification:

G06F 1328

US Classification:

710 23, 710 22, 710129

Abstract:

A memory access system is described in which local memory units on a reconfigurable chip can be used in conjunction with the system memory. Data path units on the reconfigurable chip can cause data to be swapped in and out of the local memory units as a result of calculations within the reconfigurable fabric. Alternately, a cache-like system can be used so that the data can be read into the local memory unit from the system memory units automatically.

US Patent:

6901396, May 31, 2005

Filed:

Sep 27, 2000

Appl. No.:

09/672170

Inventors:

Bradley L. Taylor - Oakland CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04L012/28

US Classification:

707 2, 37039532

Abstract:

A packed radix data system is described, the packed radix data system including packed nodes which include a base pointer and an existence field, the existence field having a number of bits which indicate the existence or non-existence of a possible child node. By counting the number of bits to the left of an indexed bit in the existence field, an offset value is determined. The offset value is combined with the base pointer value to determine the child node address.

US Patent:

7487212, Feb 3, 2009

Filed:

Dec 14, 2001

Appl. No.:

10/022325

Inventors:

Bradley Taylor - Menlo Park CA, US

Assignee:

Mirapoint Software, Inc. - Sunnyvale CA

International Classification:

G06F 13/00

US Classification:

709206

Abstract:

A method of providing a fast path message transfer agent is provided. The method includes receiving bytes of a message over a network connection and determining whether the number of bytes exceeds a predetermined threshold. If the number of bytes is less than a predetermined threshold, then the message is written only to memory. However, if the number of bytes exceeds the predetermined threshold, then some of the bytes (e. g. up to the predetermined threshold) are written to memory, wherein the remainder of the bytes are stored onto the non-volatile storage. If the message was received successfully by each destination, then the message is removed from the memory/non-volatile storage. If not, all failed destinations are identified and the message (with associated failed destinations) is stored on the nonvolatile storage for later sending.

US Patent:

7539953, May 26, 2009

Filed:

Dec 5, 2006

Appl. No.:

11/633977

Inventors:

Shay Ping Seng - San Jose CA, US
Jonathan B. Ballagh - Boulder CO, US
Roger B. Milne - Boulder CO, US
Bradley L. Taylor - Santa Cruz CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 1, 716 3, 716 17

Abstract:

Method, apparatus, and computer readable medium for circuit design is described. In one example, a model having at least one processor, at least one logic, and at least one shared memory is specified. The at least one shared memory is associated with the at least one processor. A memory map associated with the at least one shared memory and a bus adapter for coupling the memory map to the at least one processor are automatically generated.

US Patent:

7937259, May 3, 2011

Filed:

Dec 18, 2007

Appl. No.:

12/002838

Inventors:

Chi Bun Chan - San Jose CA, US
Bradley L. Taylor - San Jose CA, US
Nabeel Shirazi - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 9/455

US Classification:

703 28

Abstract:

Various embodiments of a co-simulation system are disclosed. In one embodiment, a data processing arrangement executes a simulator that simulates a first block of an electronic circuit design. A first clock source generates a first clock signal, and a second clock source generates a second clock signal. The first and second clock signals are independent one from another, and an operating frequency of the second clock signal is dynamically adjustable from a clock control interface. A programmable logic device (PLD) is configured with logic that includes a co-simulation interface clocked by the first clock signal, a second block of the electronic circuit design that is clocked by the second clock signal, and a synchronizer that controls data transmission between the co-simulation interface and the second block.

US Patent:

20020038414, Mar 28, 2002

Filed:

Sep 28, 2001

Appl. No.:

09/967855

Inventors:

Bradley Taylor - Oakland CA, US
Gary Lai - Sunnyvale CA, US

International Classification:

G06F012/00

US Classification:

711/217000

Abstract:

A reconfigurable logic system using reconfigurable functional units of the type having arithmetic logic units are associated with address generating memory units. The address generating memory units having address generators that can construct addresses for memory in the address generator memory units. This frees the reconfigurable functional unit from the need to construct a sequence of addresses for the memory unit.

US Patent:

20030052711, Mar 20, 2003

Filed:

Sep 19, 2001

Appl. No.:

09/960710

Inventors:

Bradley Taylor - Oakland CA, US
Gary Lai - Sunnyvale CA, US

International Classification:

H03K019/173

US Classification:

326/038000

Abstract:

A reconfigurable chip includes a despreader/correlator function back in order to better implement communication protocols which require despreading and/or correlation. These despreader/correlation functional blocks are used in addition to reconfigurable functional blocks having arithmetic logic units. The functions of the despreader/correlator functional blocks are preferably controlled by instructions from a local instruction memory.

US Patent:

20030140112, Jul 24, 2003

Filed:

Nov 4, 1999

Appl. No.:

09/434048

Inventors:

SATISH RAMACHANDRAN - Los Altos CA, US
Bradley Taylor - Menlo Park CA, US

International Classification:

G06F015/16

US Classification:

709/217000

Abstract:

A message system for communication of messages over a network where the messages include meta data and content data. An authentication unit authenticates users for messages from the network and a storage server unit that stores the messages. The storage server unit includes a plurality of protocol server units for processing the messages according to protocols used for the messages over the network, includes a meta-data storage unit for storing the meta data of messages, includes a content-data storage unit for string the content data of messages, and includes a manager unit for common control of the meta-data storage unit and the content-data storage unit. The manager unit includes a common addressing unit for common management of the addresses of messages at locations in the storage server unit for messages of the plurality of protocol server units and a common access control unit for controlling accesses to the locations in the storage server unit by the plurality of protocol server units.