Brian Phillip Barnes

US Patent:

6378023, Apr 23, 2002

Filed:

Jan 10, 2000

Appl. No.:

09/481005

Inventors:

David S. Christie - Austin TX
Brian C. Barnes - Round Rock TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1324

US Classification:

710260

Abstract:

An interrupt descriptor cache for a microprocessor is provided which is configured to store interrupt information associated with a plurality of interrupt vectors. Prior to fetching interrupt information from a main memory of a computer system, the microprocessor searches the interrupt descriptor cache. If the interrupt information is stored therein, the address of the interrupt service routine is formed from the stored interrupt information instead of fetching the interrupt information from main memory. The interrupt descriptor cache is additionally configured to monitory memory accesses for updates to the interrupt information stored therein. If a memory location storing interrupt information is updated, then the interrupt descriptor cache invalidates any storage locations which may be storing the information.

US Patent:

6611912, Aug 26, 2003

Filed:

Feb 4, 2000

Appl. No.:

09/498156

Inventors:

Timothy C. Maleck - Austin TX
Charles R. Boswell - Austin TX
Brian Barnes - Round Rock TX

Assignee:

Advanced Micro Devices, Inc. - Austin TX

International Classification:

G06F 124

US Classification:

713100, 713 1, 713 2, 710 8, 710 10

Abstract:

When a riser card is connected to a computer system motherboard, a storage device on the riser card will contain configuration data permitting the computer system to configure any peripheral device on the riser card. The configuration data will be treated by the BIOS in the computer system as a virtual add-on ROM thereby allowing it to execute and initialize any and all PCI configuration spaces associated with the riser card peripheral devices.

US Patent:

6823433, Nov 23, 2004

Filed:

Nov 13, 2001

Appl. No.:

10/010569

Inventors:

Brian C. Barnes - Round Rock TX
Geoffrey S. Strongin - Austin TX
Rodney W. Schmidt - Dripping Springs TX

Assignee:

Advanced Micro Devices, Inc. - Austin TX

International Classification:

G06F 1208

US Classification:

711163, 711164, 711147, 711145, 711152

Abstract:

A memory management unit (MMU) is disclosed for managing a memory storing data arranged within a plurality of memory pages. The MMU includes a security check unit (SCU) receiving a physical address generated during execution of a current instruction. The physical address resides within a selected memory page. The SCU uses the physical address to access one or more security attribute data structures located in the memory to obtain a security attribute of the selected memory page, compares a numerical value conveyed by a security attribute of the current instruction to a numerical value conveyed by the security attribute of the selected memory page, and produces an output signal dependent upon a result of the comparison. The MMU accesses the selected memory page dependent upon the output signal. The security attribute of the selected memory page may include a security context identification (SCID) value indicating a security context level of the selected memory page.

US Patent:

6842803, Jan 11, 2005

Filed:

Jul 9, 2001

Appl. No.:

09/901503

Inventors:

Rodney Schmidt - Austin TX, US
Geoffrey S. Strongin - Austin TX, US
David W. Smith - Cedar Park TX, US
Brian C. Barnes - Round Rock TX, US
Terry L. Cole - Austin TX, US
Michael Barclay - Swallowcliffe, GB

Assignee:

Advanced Micro Devices, Inc. - Austin TX

International Classification:

G06F 1312

US Classification:

710 69, 710 5, 710 29, 710 33, 709200, 709233, 711200, 341126

Abstract:

A communications system includes physical layer hardware and a processing unit. The physical layer hardware is adapted to communicate data over a communications channel in accordance with a plurality of control codes. The physical layer hardware is adapted to demodulate an incoming analog signal to generate a digital receive signal and modulate a digital transmit signal to generate an analog transmit signal. The processing unit is adapted to execute a privileged driver for interfacing with the physical layer hardware. The privileged driver includes program instructions for implementing a protocol layer to decode the digital receive signal, encode the digital transmit signal, and configure the physical layer hardware for receipt of the digital receive signal and transmission of the digital transmit signal based on the plurality of control codes. A method for configuring a transceiver includes demodulating an incoming analog signal to generate a digital receive signal based on a plurality of control codes; modulating a digital transmit signal to generate an analog transmit signal based on the control codes; and executing a privileged driver for configuring the plurality of control codes.

US Patent:

6854039, Feb 8, 2005

Filed:

Dec 5, 2001

Appl. No.:

10/005271

Inventors:

Geoffrey S. Strongin - Austin TX, US
Brian C. Barnes - Round Rock TX, US
Rodney W. Schmidt - Dripping Springs TX, US

Assignee:

Advanced Micro Devices, Inc. - Austin TX

International Classification:

G06F012/00

US Classification:

711163, 711145, 711150, 711152, 711154, 713161, 713166

Abstract:

A memory management unit (MMU) is disclosed for managing a memory storing data arranged within a multiple memory pages. The memory management unit includes a security check receiving a physical address within a selected memory page, and security attributes of the selected memory page. The security check unit uses the physical address to access one or more security attribute data structures located in the memory to obtain an additional security attribute of the selected memory page. The security check unit generates a fault signal dependent upon the security attributes of selected memory page and the additional security attribute of the selected memory page. The security attributes of the selected memory page may include a user/supervisor (U/S) bit and a read/write (R/W) bit as defined by the ×86 processor architecture. The one or more security attribute data structures may include a security attribute table directory and one or more security attribute tables. The security attribute table directory may include multiple entries, and each entry of the security attribute table directory may include a present bit and a security attribute table base address field.

US Patent:

6889308, May 3, 2005

Filed:

Jan 18, 2002

Appl. No.:

10/051448

Inventors:

Rodney W. Schmidt - Dripping Springs TX, US
Brian C. Barnes - Round Rock TX, US
Geoffrey S. Strongin - Austin TX, US

Assignee:

Advanced Micro Devices, Inc. - Austin TX

International Classification:

G06F012/00

US Classification:

711203, 711206, 711209

Abstract:

In one aspect of the present invention, an apparatus for converting a virtual address to a physical address is provided. The apparatus comprises a comparator, a first mechanism, and a second mechanism. The comparator is adapted to receive the virtual address and deliver a first signal indicating that the virtual address is outside a first preselected range, and a second signal indicating that the virtual address is within the first preselected range. The first mechanism is adapted to generate a first physical address from the virtual address in response to receiving the first signal, and the second mechanism is adapted to generate a second physical address from the virtual address in response to receiving the second signal.

US Patent:

6973566, Dec 6, 2005

Filed:

Jul 9, 2001

Appl. No.:

09/901158

Inventors:

David W. Smith - Cedar Park TX, US
Brian C. Barnes - Round Rock TX, US
Terry L. Cole - Austin TX, US
Rodney Schmidt - Austin TX, US
Geoffrey S. Strongin - Austin TX, US
Michael Barclay - Swallowcliffe, GB

Assignee:

Advanced Micro Devices, Inc. - Austin TX

International Classification:

H04L009/00
G06F015/16
H04K001/00

US Classification:

713151, 713152, 713200, 713201, 709229, 380271

Abstract:

A communications system includes a physical layer hardware unit and a processing unit. The physical layer hardware unit is adapted to communicate data over a communications channel in accordance with assigned transmission parameters. The physical layer hardware unit is adapted to receive an incoming signal over the communications channel and sample the incoming signal to generate a digital received signal. The processing unit is adapted to execute a standard mode driver in a standard mode of operation and a privileged mode driver in a privileged mode of operation. The standard mode driver includes program instructions adapted to extract control codes from the digital received signal and configure the physical layer hardware assigned transmission parameters based on the control codes. The privileged mode driver includes program instructions adapted to independently extract secure control codes from the digital received signal, determine an operational characteristic of the physical layer hardware unit, and signal a security violation in response to the operational characteristic being inconsistent with the secure control codes.

US Patent:

6985519, Jan 10, 2006

Filed:

Jul 9, 2001

Appl. No.:

09/901547

Inventors:

Brian C. Barnes - Round Rock TX, US
Terry L. Cole - Austin TX, US
David W. Smith - Cedar Park TX, US
Rodney Schmidt - Austin TX, US
Geoffrey S. Strongin - Austin TX, US
Michael Barclay - Swallowcliffe, GB

Assignee:

Advanced Micro Devices, Inc. - Austin TX

International Classification:

H04L 5/16

US Classification:

375220, 375222, 370329, 370341, 370438, 370469

Abstract:

A communications system includes a physical layer hardware unit and a processing unit. The physical layer hardware unit is adapted to receive user data over a first communications channel and control codes over a second communications channel. The physical layer hardware unit is further adapted to transmit an upstream data signal over the first communications channel based on transmission assignments defined by the control codes. The processing unit is adapted to execute a software driver for interfacing with the physical layer hardware unit. The software driver includes program instructions for implementing a protocol layer to decrypt the user data and provide upstream data to the physical layer hardware unit for generation of the upstream data signal. A method for configuring a transceiver includes receiving user data over a first communications channel; receiving control codes over a second communications channel; and transmitting an upstream signal over the first communications channel based on transmission assignments defined by the control codes.