Brian M Cabral

US Patent:

7385607, Jun 10, 2008

Filed:

Sep 10, 2004

Appl. No.:

10/938042

Inventors:

Rui M. Bastos - Porto Alegre, BR
Karim M. Abdalla - Menlo Park CA, US
Christian Rouet - San Rafael CA, US
Michael J. M. Toksvig - Palo Alto CA, US
Johnny S. Rhoades - Durham NC, US
Roger L. Allen - San Jose CA, US
Emmett M. Kilgariff - San Jose CA, US
Gary M. Tarolli - Concord MA, US
Brian Cabral - San Jose CA, US
Craig Michael Wittenbrink - Palo Alto CA, US
Sean J. Treichler - Mountain View CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06F 15/16
G06F 15/80
G06T 1/20

US Classification:

345502, 345505, 345506

Abstract:

A scalable shader architecture is disclosed. In accord with that architecture, a shader includes multiple shader pipelines, each of which can perform processing operations on rasterized pixel data. Shader pipelines can be functionally removed as required, thus preventing a defective shader pipeline from causing a chip rejection. The shader includes a shader distributor that processes rasterized pixel data and then selectively distributes the processed rasterized pixel data to the various shader pipelines, beneficially in a manner that balances workloads. A shader collector formats the outputs of the various shader pipelines into proper order to form shaded pixel data. A shader instruction processor (scheduler) programs the individual shader pipelines to perform their intended tasks. Each shader pipeline has a shader gatekeeper that interacts with the shader distributor and with the shader instruction processor such that pixel data that passes through the shader pipelines is controlled and processed as required.

US Patent:

7408553, Aug 5, 2008

Filed:

Dec 15, 2005

Appl. No.:

11/305483

Inventors:

Michael J. M. Toksvig - Palo Alto CA, US
Edward A. Hutchins - Mountain View CA, US
Brian Cabral - San Jose CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06T 11/40

US Classification:

345441, 345423

Abstract:

Systems and methods for identifying pixels that are inside a two-dimensional path may be used to fill the path. The path is segmented and a point in space is identified that is used to generate a triangle fan, where each triangle in the fan is formed by one of the segments of the path and the point. Locations in a winding buffer are updated for each pixel that is within a triangle of the triangle fan. The resulting winding buffer indicates the pixels that are inside the two-dimensional path. The winding buffer may be used to fill the path.

US Patent:

7600155, Oct 6, 2009

Filed:

Dec 13, 2005

Appl. No.:

11/302950

Inventors:

John R. Nickolls - Los Altos CA, US
Roger L. Allen - Lake Oswego OR, US
Brian K. Cabral - San Jose CA, US
Brett W. Coon - San Jose CA, US
Robert C. Keller - Palo Alto CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06F 11/00

US Classification:

714 38

Abstract:

A system has a graphics processing unit with a processor to monitor selected criteria and circuitry to initiate the storage of execution state information when the selected criteria reaches a specified state. A memory stores execution state information. A central processing unit executes a debugging program to analyze the execution state information.

US Patent:

7711990, May 4, 2010

Filed:

Dec 13, 2005

Appl. No.:

11/302952

Inventors:

John R. Nickolls - Los Altos CA, US
Roger L. Allen - Lake Oswego OR, US
Brian K. Cabral - San Jose CA, US
Brett W. Coon - San Jose CA, US
Robert C. Keller - Palo Alto CA, US

Assignee:

Nvidia Corporation - Santa Clara CA

International Classification:

G06F 11/00

US Classification:

714 37

Abstract:

A system includes a graphics processing unit with a processor responsive to a debug instruction that initiates the storage of execution state information. A memory stores the execution state information. A central processing unit executes a debugging program to analyze the execution state information.

US Patent:

7852340, Dec 14, 2010

Filed:

Dec 14, 2007

Appl. No.:

11/957358

Inventors:

Rui M. Bastos - Rua Luzitana, BR
Karim M. Abdalla - Menlo Park CA, US
Christian Rouet - San Rafael CA, US
Michael J.M. Toksvig - Palo Alto CA, US
Johnny S Rhoades - Durham NC, US
Roger L. Allen - San Jose CA, US
Emmett M. Kilgariff - San Jose CA, US
Gary M. Tarolli - Concord MA, US
Brian Cabral - San Jose CA, US
Craig Michael Wittenbrink - Palo Alto CA, US
Sean J. Treichler - Mountain View CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06F 15/80
G06T 15/50
G06T 15/00

US Classification:

345505, 345426, 345522

Abstract:

A scalable shader architecture is disclosed. In accord with that architecture, a shader includes multiple shader pipelines, each of which can perform processing operations on rasterized pixel data. Shader pipelines can be functionally removed as required, thus preventing a defective shader pipeline from causing a chip rejection. The shader includes a shader distributor that processes rasterized pixel data and then selectively distributes the processed rasterized pixel data to the various shader pipelines, beneficially in a manner that balances workloads. A shader collector formats the outputs of the various shader pipelines into proper order to form shaded pixel data. A shader instruction processor (scheduler) programs the individual shader pipelines to perform their intended tasks. Each shader pipeline has a shader gatekeeper that interacts with the shader distributor and with the shader instruction processor such that pixel data that passes through the shader pipelines is controlled and processed as required.

US Patent:

8004522, Aug 23, 2011

Filed:

Aug 7, 2007

Appl. No.:

11/890839

Inventors:

Michael J. M. Toksvig - Palo Alto CA, US
Brian K. Cabral - San Jose CA, US
Edward A. Hutchins - Mountain View CA, US
Gary C. King - San Jose CA, US
Christopher D. S. Donham - San Mateo CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06T 15/50
G09G 5/00

US Classification:

345426, 345581

Abstract:

The boundary of a surface can be represented as a series of line segments. A number of polygons are successively superimposed onto the surface. The polygons utilize a common reference point and each of the polygons has an edge that coincides with one of the line segments. Coverage bits are associated with respective sample locations within a pixel. A value of a coverage bit is changed each time a sample location associated with the coverage bit is covered by one of the polygons. Final values of the coverage bits are buffered after all of the polygons have been processed. The values of the coverage bits can be used when the surface is subsequently rendered.

US Patent:

20110096190, Apr 28, 2011

Filed:

Dec 30, 2009

Appl. No.:

12/650202

Inventors:

Amnon Silverstein - Palo Alto CA, US
Brian Cabral - San Jose CA, US

Assignee:

NVIDIA CORPORATION - Santa Clara CA

International Classification:

H04N 9/73

US Classification:

3482231, 348E09052

Abstract:

Embodiments of the claimed subject matter are directed to methods for automatic white balancing in an image-capture device. In one embodiment, given an estimated illuminant color (e.g., derived from the Gray World method), a more optimal illuminant color can be found by projecting this point to a plot of common illuminants to determine the closest point on the plot of common illuminants. Once the closest point of the plot of common illuminants is derived, the actual image (e.g., pixel) data of the scene is adjusted by the value of the closest point on the plot of common illuminants so that the light is normalized for the scene.

US Patent:

20180300590, Oct 18, 2018

Filed:

Apr 18, 2017

Appl. No.:

15/490895

Inventors:

- Menlo Park CA, US
Michael John Toksvig - Palo Alto CA, US
Brian Keith Cabral - San Jose CA, US

International Classification:

G06K 9/62
G06T 7/55
H04N 5/232

Abstract:

A camera system captures images from a set of cameras to generate binocular panoramic views of an environment. The cameras are oriented in the camera system to maximize the minimum number of cameras viewing a set of randomized test points. To calibrate the system, matching features between images are identified and used to estimate three-dimensional points external to the camera system. Calibration parameters are modified to improve the three-dimensional point estimates. When images are captured, a pipeline generates a depth map for each camera using reprojected views from adjacent cameras and an image pyramid that includes individual pixel depth refinement and filtering between levels of the pyramid. The images may be used generate views of the environment from different perspectives (relative to the image capture location) by generating depth surfaces corresponding to the depth maps and blending the depth surfaces.