Brian M Case

US Patent:

49263234, May 15, 1990

Filed:

Mar 3, 1988

Appl. No.:

7/163917

Inventors:

Gigy Baror - Austin TX
Brian W. Case - Sunnyvale CA
Rod G. Fleck - Munich, DE
Philip M. Freidin - Sunnyvale CA
Smeeta Gupta - Saratoga CA
William M. Johnson - San Jose CA
Cheng-Gang Kong - Saratoga CA
Ole H. Moller - Lyngby, DK
Timothy A. Olson - Sunnyvale CA
David I. Sorensen - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 940
G06F 900

US Classification:

364200

Abstract:

A streamlined instruction processor processes data in response to a program composed of prespecified instructions in pipeline cycles. The processor comprises an instruction fetch unit, including an instruction interface adapted for connection to an instruction memory and for fetching instructions from the instruction memory. The instruction fetch unit includes an instruction prefetch buffer coupled to the instruction interface for buffering a sequence of instructions supplied to the instruction interface. A branch target cache is coupled with the prefetch buffer for storing sets of instructions retrieved from a corresponding set of locations in the instruction memory, having sequential instruction addresses. The first instruction in each such set is a branch target instruction in the program. In addition, an execution unit including a data interface adapted for connection to the data memory, executes the instructions in pipeline cycles.