Brian P Chesney

US Patent:

20170180853, Jun 22, 2017

Filed:

Apr 18, 2016

Appl. No.:

15/131886

Inventors:

- Edinburgh, GB
James Thomas DEAS - Edinburgh, GB
Stephen T. HODAPP - Austin TX, US
Brian Parker CHESNEY - Bee Cave TX, US

Assignee:

Cirrus Logic International Semiconductor Ltd. - Edinburgh

International Classification:

H04R 3/00
H04R 29/00

Abstract:

A system may include control circuitry for detecting a plosive event associated with a microphone transducer and in response to the plosive event, causing restoration of acoustic sense operation of the microphone transducer and a processing circuit associated with the microphone transducer. A system for configuring a filter having at least two frequency response configurations to achieve an effective frequency response configuration intermediate to the at least two frequency response configurations may include control circuitry for rapidly switching between the at least two frequency response configurations such that a weighted average frequency response of the filter corresponds to the effective frequency response configuration.

US Patent:

20150380005, Dec 31, 2015

Filed:

Jun 22, 2015

Appl. No.:

14/745795

Inventors:

- Austin TX, US
Brian Parker Chesney - Bee Cave TX, US

International Classification:

G10L 19/04
H03M 3/00

Abstract:

A system may include a delta-sigma analog-to-digital converter and a digital compression circuit. The delta-sigma analog-to-digital converter may include a loop filter having a loop filter input configured to receive an input signal and generate an intermediate signal responsive to the input signal, a multi-bit quantizer configured to quantize the intermediate signal into an uncompressed digital output signal, and a feedback digital-to-analog converter having a feedback output configured to generate a feedback output signal responsive to the uncompressed digital output signal in order to combine the input signal and the feedback output signal at the loop filter input. The digital compression circuit may be configured to receive the uncompressed digital output signal and compress the uncompressed digital output signal into a compressed digital output signal having fewer quantization levels than that of the uncompressed digital output signal.

US Patent:

20150356982, Dec 10, 2015

Filed:

Sep 25, 2014

Appl. No.:

14/655396

Inventors:

Brian CHESNEY - Pittsburgh PA, US
Brian Chesney - Pittsburgh PA, US

Assignee:

Robert Bosch GmbH - Stuttgart

International Classification:

G10L 25/78
G10L 17/22

Abstract:

A speech detection circuit (SDC). The SDC includes a first-in, first-out (FIFO) memory array, a multiplier, a summer, a fast Fourier transformer, a counter, an RMS comparator, and a sparsity comparator. The FIFO stores a plurality of data samples. The multiplier squares the data samples. The summer sums the plurality of squared data samples. The fast Fourier transformer performs an FFT on the plurality of data samples. The counter counts a quantity of the plurality of data samples that exceed a spectral threshold. The RMS comparator compares the summed plurality of squared data samples to an RMS threshold, the quantity of which are compared to a sparsity threshold. The SDC then outputs a wakeup signal when the summed plurality of squared data samples exceeds the RMS threshold and the quantity of the plurality of data samples that exceed the spectral threshold is less than the sparsity threshold.