Brian L Collins

US Patent:

6587996, Jul 1, 2003

Filed:

Jun 12, 2000

Appl. No.:

09/593600

Inventors:

Brian M. Collins - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1750

US Classification:

716 4, 716 5, 716 6

Abstract:

A device and method to test a circuit in a chip that has memory embedded in the chip using a scan chain. This device and method generates a known signal simultaneously to a bypass circuit and the memory onboard the chip. The bypass circuit uses a series of exclusive OR gates, a flip-flop, and a multiplexer to receive the known signal. The exclusive OR gates reduce the number of signals input so that they match the number of signals output by memory. A flip-flop is used to store the data received from the exclusive OR gates and transfer it to a multiplexer. The multiplexer receives data from memory and the flip-flop and selects which data to pass on in the circuit. When a scan test is being run on the circuit the multiplexer passes on only the data from the flip-flop. When a scan test is not being run the multiplexer only passes on the data from memory. This device and method allows for circuits to be tested using a scan chain that could not otherwise be tested due to the presence of memory embedded in the chip.

US Patent:

6625768, Sep 23, 2003

Filed:

Mar 29, 2000

Appl. No.:

09/537398

Inventors:

Dean S. Susnow - Portland OR
Brian M. Collins - Aloha OR
Tom E. Burton - Vancouver WA
Dominic J. Gasbarro - Forest Grove OR
Brian M. Leitner - Hillsboro OR
Ni Jie - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G01R 3128

US Classification:

714729

Abstract:

A test bus architecture for testing an integrated circuit having a plurality of agents includes providing both a test block select signal and test function select signal to a plurality of select decoders respectively disposed in each of the plurality of agents. The test block select signal has a number of states at least equal to the number of agents and the test function select signal at least equal to a maximum number of internal signal groups of any one of the agents, each select decoder having at least one internal signal group which is outputted from circuitry to be tested within the agent of the select decoder. An output from each of the select decoders is fed to a test bus output such that a selected internal signal group is outputted to the test bus output upon the agent of the selected signal group being selected by the state of the test block select signal and the selected signal group being selected by the state of the test function select signal by the select decoder.

US Patent:

6671837, Dec 30, 2003

Filed:

Jun 6, 2000

Appl. No.:

09/588005

Inventors:

Brian M. Collins - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 2900

US Classification:

714719, 365201

Abstract:

A device and method to test memory embedded in a chip in which the memory is not directly accessible from a tester external to the chip. The device and method uses a state machine embedded in control circuitry of the chip to execute software to test the memory embedded on the chip. The software in turn employs a row and column address generator connected to the state machine to access each memory location in the memory embedded in the chip. A data generator is also used by the software to generate and write data to memory locations specified by the row and column address generator. Several multiplexers are used to accept data from the data generator and pass the data to the memory embedded in the chip. These multiplexers act to enable reads and writes to memory when a memory test is performed or to enable normal reads and writes to memory when normal operations of the chip are executed. A data comparator is used to determine if the memory is working properly.

US Patent:

6718453, Apr 6, 2004

Filed:

Mar 26, 2001

Appl. No.:

09/816078

Inventors:

Brian M. Collins - Aloha OR
Dick Reohr - Hillsboro OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1210

US Classification:

711206

Abstract:

A method and apparatus for non-contiguous translation protection table that includes one or more first registers, two or more second registers, an address translator, and a detector. Each first register contains a value denoting a size of each of two or more blocks of memory. Each second register contains a value denoting the starting physical address of an associated one of the two or more blocks of memory. The address translator receives a virtual address and translates the virtual address to a physical address of one of the two or more blocks of memory. The detector detects whether the received virtual address is outside of the range of the two or more blocks of memory. The blocks of memory may be translation protection tables that reside in physically non-contiguous memory locations.

US Patent:

6842840, Jan 11, 2005

Filed:

Feb 27, 2001

Appl. No.:

09/793751

Inventors:

Brian M. Collins - Aloha OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 800
G06F 1200

US Classification:

711172, 711103, 365236, 36518505, 36518535

Abstract:

A system for determining whether a memory is connected to a controller in a node of a data network. In order to utilize non-volatile memory elsewhere in the system, it is possible to eliminate the EEPROM which is normally connected to the controller. In order to indicate that the EEPROM is deliberately missing, a pull-up resistor connected to a voltage source is connected to the chip select signal line which normally runs between the controller and the EEPROM. If a high signal is received, the controller knows that the EEPROM is deliberately missing and that non-volatile memory will be provided elsewhere in the system.

US Patent:

7363389, Apr 22, 2008

Filed:

Mar 29, 2001

Appl. No.:

09/819997

Inventors:

Brian M. Collins - Aloha OR, US
Frank L. Berry - North Plains OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 15/16

US Classification:

709250, 370310, 370352, 370353, 370354, 370463

Abstract:

A method and apparatus for enhancing channel adapter performance that includes a host interface, a link interface, a packet processing engine, an address translation engine, and a completion queue engine. The host interface is connected to a memory by a local bus. The memory contains one or more completion queues and an event queue. The link interface is connected to a network. The packet processing engine moves data between the host interface and the link interface. The address translation engine translates a virtual address into a physical address of a translation protection table in the memory. The completion queue engine processes completion requests from the packet processing engine by writing the appropriate completion queue and/or event queue. The packet processing engine is not impacted by any address translation functionality, completion queue accesses, or event queue accesses thereby significantly enhancing the performance of a channel adapter.

US Patent:

20040168038, Aug 26, 2004

Filed:

Feb 27, 2004

Appl. No.:

10/788777

Inventors:

Brian Collins - Aloha OR, US
Dick Reohr - Hillsboro OR, US

Assignee:

Intel Corporation

International Classification:

G06F012/08

US Classification:

711/206000

Abstract:

A method and apparatus for non-contiguous translation protection table that includes one or more first registers, two or more second registers, an address translator, and a detector. Each first register contains a value denoting a size of each of two or more blocks of memory. Each second register contains a value denoting the starting physical address of an associated one of the two or more blocks of memory. The address translator receives a virtual address and translates the virtual address to a physical address of one of the two or more blocks of memory. The detector detects whether the received virtual address is outside of the range of the two or more blocks of memory. The blocks of memory may be translation protection tables that reside in physically non-contiguous memory locations.

US Patent:

62980068, Oct 2, 2001

Filed:

Dec 30, 1999

Appl. No.:

9/476302

Inventors:

Richard D. Reohr - Hillsboro OR
Brian M. Collins - Aloha OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 800

US Classification:

365236

Abstract:

The present invention automatically determines the size of an EEPROM in a circuit. A controller is connected to the EEPROM with both a "data to" the EEPROM connection and a "data from" the EEPROM connection. The controller begins to send logical low address bits over the "data to" the EEPROM connection. After each address bit is transmitted, the controller increments the value of a counter. The controller continually monitors the data from the EEPROM connection to determine when the EEPROM has been successfully addressed. Once the EEPROM receives the appropriate number of address bits to fully address the first address location, the EEPROM drives the "data from" connection low. The controller then uses the value of the counter to determine the size of the EEPROM. The controller may either calculate the size of the EEPROM or use the value of the counter in a look-up table.