Brian K Gilmore

US Patent:

8420554, Apr 16, 2013

Filed:

May 3, 2010

Appl. No.:

12/772627

Inventors:

Brian Lawrence Gilmore - Foristell MO, US

Assignee:

MEMC Electronic Materials, Inc. - St. Peters MO

International Classification:

H01L 21/324

US Classification:

438795, 438907, 257E21497, 269289 R

Abstract:

A wafer support ring and a method of using the same are disclosed herein. The support ring supports a wafer during a first processing operation. A top surface of the support ring is in contact with a first plurality of locations on a surface of the wafer during the first processing operation. A second wafer support structure is used to support the wafer during a second processing operation. A top surface of the second wafer support structure is in contact with a second, different plurality of locations on the surface of the wafer during the second processing operation. The wafer support ring may also have an outer lip disposed about an outer periphery of the support ring that has a depth such that it does not form part of the top surface of the support ring.

US Patent:

8042697, Oct 25, 2011

Filed:

Jun 30, 2008

Appl. No.:

12/165048

Inventors:

Brian Lawrence Gilmore - Foristell MO, US
Lance G. Hellwig - Florissant MO, US

Assignee:

MEMC Electronic Materials, Inc. - St. Peters MO

International Classification:

A47G 19/08

US Classification:

211 4118

Abstract:

A support for a semiconductor wafer includes a plate having a support surface for supporting the wafer and a recessed surface spaced from the support surface and spaced from the wafer. A plurality of holes extends from the recessed surface, and the support surface is free of holes to inhibit contamination of the wafer.

US Patent:

20100098519, Apr 22, 2010

Filed:

Oct 17, 2008

Appl. No.:

12/253664

Inventors:

Larry Wayne Shive - St. Charles MO, US
Brian Lawrence Gilmore - Foristell MO, US
Timothy John Snyder - Florissant MO, US

Assignee:

MEMC ELECTRONIC MATERIALS, INC. - St. Peters MO

International Classification:

H01L 21/687

US Classification:

414587, 414586

Abstract:

A wafer support for supporting a semiconductor wafer during a process including varied temperature. The wafer support includes a body having a top surface adapted to receive the semiconductor wafer so a portion of the top surface supports the wafer. The top surface has a recessed area including an inclined surface rising from a bottom of the recessed area. The inclined surface has an incline angle that is no more than about ten degrees.

US Patent:

20100304022, Dec 2, 2010

Filed:

Jul 29, 2010

Appl. No.:

12/846510

Inventors:

Larry W. Shive - St. Charles MO, US
Brian L. Gilmore - O'Fallon MO, US

Assignee:

MEMC ELECTRONIC MATERIALS, INC. - St. Peters MO

International Classification:

B05D 1/38
C23C 16/02

US Classification:

427203, 42725518

Abstract:

A method is disclosed for sandblasting a wafer support platform to create a surface having a uniform roughness. Contaminants become embedded in the surface during the sandblasting procedure. A layer is applied over the surface to isolate the contaminants from a supported wafer while maintaining the uniform roughness.

US Patent:

20080041798, Feb 21, 2008

Filed:

Jun 22, 2007

Appl. No.:

11/767198

Inventors:

Brian L. Gilmore - O'Fallon MO, US
Larry W. Shive - St. Charles MO, US

Assignee:

MEMC ELECTRONIC MATERIALS, INC. - St. Peters MO

International Classification:

B05C 13/00
A47G 19/08

US Classification:

211 4118, 118500, 414938

Abstract:

A platform for supporting a semiconductor wafer includes a body with channel having spaced apart first and second edge margins in contiguous relationship with a top surface of the body. At least one of the edge margins is generally convex along at least a portion of the channel.

US Patent:

20080156260, Jul 3, 2008

Filed:

Dec 27, 2006

Appl. No.:

11/616485

Inventors:

Larry W. Shive - St. Charles MO, US
Brian L. Gilmore - O'Fallon MO, US

Assignee:

MEMC ELECTRONIC MATERIALS, INC. - St. Peters MO

International Classification:

C23C 16/02
B05C 13/00

US Classification:

118500, 42725528

Abstract:

A wafer support platform is sandblasted with silicon-containing particles to create a surface with uniform roughness. Contaminants become embedded in the surface during the sandblasting procedure. A layer is applied over the surface to isolate the contaminants from a support wafer while maintaining the uniform roughness.

US Patent:

20070221609, Sep 27, 2007

Filed:

May 30, 2007

Appl. No.:

11/755472

Inventors:

Larry Shive - St. Charles MO, US
Brian Gilmore - O'Fallon MO, US

Assignee:

MEMC ELECTRONIC MATERIALS, INC. - St. Peters MO

International Classification:

C23F 1/00

US Classification:

216002000

Abstract:

Processes for the purification of silicon carbide structures, including silicon carbide coated silicon carbide structures, are disclosed. The processes described can reduce the amount of iron contamination in a silicon carbide structure by 100 to 1000 times. After purification, the silicon carbide structures are suitable for use in high temperature silicon wafer processing.

US Patent:

20050250297, Nov 10, 2005

Filed:

May 7, 2004

Appl. No.:

10/840854

Inventors:

Larry Shive - St. Charles MO, US
Brian Gilmore - O'Fallon MO, US

International Classification:

H01L021/335
H01L021/8232
H01L021/322
H01L021/311

US Classification:

438471000, 438476000, 438694000, 438906000

Abstract:

A process for removing a contaminant selected from among copper, nickel, and a combination thereof from a silicon wafer having a surface and an interior. The process comprises cooling the silicon wafer in a controlled atmosphere from a temperature at or above an oxidation initiation temperature and initiating a flow of an oxygen-containing atmosphere at said oxidation initiation temperature to create an oxidizing ambient around the silicon wafer surface to form an oxide layer on the silicon wafer surface and a strain layer at an interface between the oxide layer and the silicon wafer interior. The cooling of the wafer is also controlled to permit diffusion of atoms of the contaminant from the silicon wafer interior to the strain layer. Then the silicon wafer is then cleaned to remove the oxide layer and the strain layer, thereby removing said contaminant having diffused to the strain layer.