Brian N Greene

US Patent:

7132322, Nov 7, 2006

Filed:

May 11, 2005

Appl. No.:

10/908411

Inventors:

Brian Joseph Greene - Yorktown Heights NY, US
Kern Rim - Yorktown Heights NY, US
Clement Wann - Carmel NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/8238
H01L 21/8242
H01L 21/336

US Classification:

438199, 438242, 438258, 257E51005, 257E29137

Abstract:

Form a dielectric layer on a semiconductor substrate. Deposit an amorphous Si film or a poly-Si film on the dielectric layer. Then deposit a SiGe amorphous-Ge or polysilicon-Ge thin film theteover. Pattern and etch the SiGe film using a selective etch leaving the SiGe thin film intact in a PFET region and removing the SiGe film exposing the top surface of the Si film in an NFET region. Anneal to drive Ge into the Si film in the PFET region. Deposit a gate electrode layer covering the SiGe film in the PFET region and cover the exposed portion of the Si film in the NFET region. Pattern and etch the gate electrode layer to form gates. Form FET devices with sidewall spacers and source regions and drains regions in the substrate aligned with the gates.

US Patent:

7205639, Apr 17, 2007

Filed:

Mar 9, 2005

Appl. No.:

11/076080

Inventors:

Matthias Hierlemann - Fishkill NY, US
Chun-Yung Sung - Poughkeepsie NY, US
Brian J. Greene - Yorktown Heights NY, US
Manfred Eller - Wappingers Falls NY, US

Assignee:

Infineon Technologies AG - Munich
International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/04
H01L 31/00

US Classification:

257628, 257369, 257255, 438199

Abstract:

Integrated circuits are oriented on a substrate at an angle that is rotated between 0 to 45 degrees from a direction parallel or perpendicular to a preferred crystalline plane direction, such as the cleavage plane, of the substrate. Parameters such as stress and mobility of transistors may be optimized by adjusting the angle of rotation of the substrate. For a rotated substrate CMOS device design, other stress control measures may be used, such as a stress control or tensile liner, over an NMOS transistor, PMOS transistor, or both, to further adjust the stress and improve performance.

US Patent:

7317204, Jan 8, 2008

Filed:

Sep 2, 2005

Appl. No.:

11/218397

Inventors:

Min-chul Sun - Suwon-si, KR
Ja-hum Ku - Seongnam-si, KR
Brian J. Greene - Yorktown Heights NY, US
Manfred Eller - Wappingers Falls NY, US
Wee Lang Tan - Beacon NY, US
Zhijiong Luo - Carmel NY, US

Assignee:

Samsung Electronics Co., Ltd. - Suwon-Si, Geyonggi-do

International Classification:

H01L 23/58

US Classification:

257 48, 438 17, 438 18, 257E21521, 257E21522

Abstract:

A test structure of a semiconductor device is provided. The test structure includes a semiconductor substrate, a transistor which includes a gate electrode formed on first and second active regions defined within the semiconductor substrate, and first and second junction regions which are arranged at both sidewalls of the gate electrode to reside within the first and second active regions and are silicided, and first and second pads through which electrical signals are applied to the silicided first and second junction regions and detected and which are formed on the same level as the gate electrode or the semiconductor substrate.

US Patent:

7365399, Apr 29, 2008

Filed:

Jan 17, 2006

Appl. No.:

11/333074

Inventors:

Joel P. de Souza - Putnam Valley NY, US
Keith E. Fogel - Hopewell Junction NY, US
Brian J. Greene - Danbury CT, US
Devendra K. Sadana - Pleasantville NY, US
Haining S. Yang - Wappingers Falls NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/76
H01L 29/94
H01L 31/00

US Classification:

257368, 438409

Abstract:

A semiconducting material that has all the advantages of prior art SOI substrates including, for example, low parasitic capacitance and leakage, without having floating body effects is provided. More specifically, the present invention provides a Semiconductor-on-Pores (SOP) material that includes a top semiconductor layer and a bottom semiconductor layer, wherein the semiconductor layers are separated in at least one region by a porous semiconductor material. Semiconductor structures including the SOP material as a substrate as well as a method of fabricating the SOP material are also provided. The method includes forming a p-type region with a first semiconductor layer, converting the p-type region to a porous semiconductor material, sealing the upper surface of the porous semiconductor material by annealing, and forming a second semiconductor layer atop the porous semiconductor material.

US Patent:

7405131, Jul 29, 2008

Filed:

Jul 16, 2005

Appl. No.:

11/182681

Inventors:

Yung Fu Chong - Singapore, SG
Brian Joseph Greene - Yorktown Heights NY, US

Assignee:

Chartered Semiconductor Manufacturing, Ltd. - Singapore
International Business Machines Corporation (IBM) - Armonk NY

International Classification:

H01L 21/20
H01L 21/336

US Classification:

438300, 438285, 438299, 438303, 438471, 438518, 257E21193, 257E21402, 257E21131

Abstract:

The example embodiments disclose devices and methods to prevent silicide strapping of the Source/Drain to Body in semiconductor devices with S/D stressor. We provide isolation regions in the substrate and a gate structure over the substrate. We form recesses in the substrate adjacent to the gate structure with disposable spacers and adjacent to the isolation regions. We provide stressor regions filling the recesses. The stress region can have a pit adjacent the isolation regions. We form stressor spacers at least partially in the pit on the sidewalls of the stressor regions. We form silicide regions over the stressor regions. The spacer on the stressor regions sidewalls inhibit the formation of silicide at the stressor region edge during the silicide process, thus preventing silicide strapping of the Source/Drain to Body.

US Patent:

7442618, Oct 28, 2008

Filed:

Jul 16, 2005

Appl. No.:

11/182682

Inventors:

Yung Fu Chong - Singapore, SG
Brian Joseph Greene - Yorktown Heights NY, US
Siddhartha Panda - Beacon NY, US
Nivo Rovedo - Lagrangeville NY, US

Assignee:

Chartered Semiconductor Manufacturing, Ltd - Singapore

International Classification:

H01L 21/44

US Classification:

438424, 438410, 438435, 438437, 257E21549

Abstract:

Structures and methods for forming keyhole shaped regions for isolation and/or stressing the substrate are shown. In a first embodiment, we form an inverted keyhole shaped trench in the substrate in the first opening preferably using a two step etch. Next, we fill the inverted keyhole trench with a material that insulates and/or creates stress on the sidewalls of the inverted keyhole trench. In a second embodiment, we form a keyhole stressor region adjacent to the gate and isolation structures. The keyhole stressor region creates stress near the channel region of the FET to improve FET performance. The stressor region can be filled with an insulator or a semiconductor material.

US Patent:

7449374, Nov 11, 2008

Filed:

Feb 23, 2007

Appl. No.:

11/710382

Inventors:

Matthias Hierlemann - Fishkill NY, US
Chun-Yung Sung - Poughkeepsie NY, US
Brian J. Greene - Yorktown Heights NY, US
Manfred Eller - Wappingers Falls NY, US

Assignee:

Infineon Technologies AG - Munich
Internatioanl Business Machines Corporation - Armonk NY

International Classification:

H01L 21/84

US Classification:

438150, 438198, 438199, 438166, 438178, 257E29004

Abstract:

Integrated circuits are oriented on a substrate at an angle that is rotated between 5 to 40 degrees from a direction parallel or perpendicular to a preferred crystalline plane direction, such as the cleavage plane, of the substrate. Parameters such as stress and mobility of transistors may be optimized by adjusting the angle of rotation of the substrate. For a rotated substrate CMOS device design, other stress control measures may be used, such as a stress control or tensile liner, over an NMOS transistor, PMOS transistor, or both, to further adjust the stress and improve performance.

US Patent:

7501651, Mar 10, 2009

Filed:

Oct 5, 2005

Appl. No.:

11/243595

Inventors:

Min-chul Sun - Suwon-si, KR
Ja-hum Ku - Seongnam-si, KR
Brian J. Greene - Yorktown Heights NY, US
Manfred Eller - Wappingers Falls NY, US
Roman Knoefler - Fishkill NY, US
Zhijiong Luo - Carmel NY, US

Assignee:

Samsung Electronics Co., Ltd. - Suwon-Si

International Classification:

H01L 23/58

US Classification:

257 48

Abstract:

A test structure of a semiconductor device with improved test reliability is provided. The test structure includes first and second active regions which are electrically isolated from each other and on which silicided first and second junction regions are formed, respectively, a semiconductor substrate or a well which is formed on lower parts of the first and second junction regions and has a conductivity type different from the first and second junction regions, and first and second pads through which an electrical signal is applied to the first and second junction regions and detected, and which are formed on the same level as a lower part of a metal layer or on the same level as the semiconductor substrate.