Brian M Greene

US Patent:

7410852, Aug 12, 2008

Filed:

Apr 21, 2006

Appl. No.:

11/408522

Inventors:

Scott D. Allen - Ledgewood NJ, US
Cyril Cabral, Jr. - Mahopac NY, US
Kevin K. Dezfulian - Mount Kisco NY, US
Brian J. Greene - Danbury CT, US
Rajarao Jammy - Hopewell Junction NY, US
Christian Lavoie - Ossinging NY, US
Zhijiong Luo - Carmel NY, US
Hung Ng - New Milford NJ, US
Chun-Yung Sung - Poughkeepsie NY, US
Clement H. Wann - Carmel NY, US
Huilong Zhu - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/8234
H01L 21/42

US Classification:

438197, 438535, 257E21028, 257E21622

Abstract:

An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region adjacent the metal gate. Another opto-thermal annealing method may be used for simultaneously opto-thermally annealing: (1) a silicon layer and a silicide forming metal layer to form a fully silicided gate; and (2) a source/drain region to form an annealed source/drain region. An additional opto-thermal annealing method may use a thermal insulator layer in conjunction with a thermal absorber layer to selectively opto-thermally anneal a silicon layer and a silicide forming metal layer to form a fully silicide gate.

US Patent:

7989298, Aug 2, 2011

Filed:

Jan 25, 2010

Appl. No.:

12/692859

Inventors:

Kevin K. Chan - Staten Island NY, US
Brian J. Greene - Wappingers Falls NY, US
Judson R. Holt - Wappingers Falls NY, US
Jeffrey B. Johnson - Essex Junction NY, US
Thomas S. Kanarsky - Hopewell Junction NY, US
Jophy S. Koshy - Wappingers Falls NY, US
Kevin McStay - Hopewell Junction NY, US
Johan W. Weijtmans - Hopewell Junction NY, US
Frank B. Yang - Mahwah NJ, US

Assignee:

International Business Machines Corporation - Armonk NY
Advanced Micro Devices, Inc - Sunnyvale CA

International Classification:

H01L 21/336
H01L 21/76

US Classification:

438300, 438222, 438285, 438429, 257E2143, 257E21409

Abstract:

A semiconductor device and a method of making the device are provided. The method can include forming a gate conductor overlying a major surface of a monocrystalline semiconductor region and forming first spacers on exposed walls of the gate conductor. Using the gate conductor and the first spacers as a mask, at least extension regions are implanted in the semiconductor region and dummy spacers are formed extending outward from the first spacers. Using the dummy spacers as a mask, the semiconductor region is etched to form recesses having at least substantially straight walls extending downward from the major surface to a bottom surface, such that a substantial angle is defined between the bottom surface and the walls. Subsequently, the process is continued by epitaxially growing regions of stressed monocrystalline semiconductor material within the recesses. Then the dummy spacers are removed and the transistor can be completed by forming source/drain regions of the transistor that are at least partially disposed in the stressed semiconductor material regions.

US Patent:

8039331, Oct 18, 2011

Filed:

May 14, 2008

Appl. No.:

12/120286

Inventors:

Scott D. Allen - Ledgewood NJ, US
Cyril Cabral, Jr. - Mahopac NY, US
Kevin K. Dezfulian - Mount Kisco NY, US
Brian J. Greene - Yorktown Heights NY, US
Rajarao Jammy - Hopewell Junction NY, US
Christian Lavoie - Ossining NY, US
Zhijiong Luo - Carmel NY, US
Hung Ng - New Milford NJ, US
Chun-Yung Sung - Poughkeepsie NY, US
Clement H. Wann - Carmel NY, US
Huilong Zhu - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/336
H01L 21/8234

US Classification:

438197, 438199, 257E21632

Abstract:

An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region adjacent the metal gate. Another opto-thermal annealing method may be used for simultaneously opto-thermally annealing: (1) a silicon layer and a silicide forming metal layer to form a fully silicided gate; and (2) a source/drain region to form an annealed source/drain region. An additional opto-thermal annealing method may use a thermal insulator layer in conjunction with a thermal absorber layer to selectively opto-thermally anneal a silicon layer and a silicide forming metal layer to form a fully silicide gate.

US Patent:

20100213206, Aug 26, 2010

Filed:

Sep 7, 2007

Appl. No.:

12/377288

Inventors:

Brian M. Greene - North Easton MA, US

International Classification:

B65D 90/00

US Classification:

220752

Abstract:

A detachable handle for a child's sippy cup. The sippy cup includes a cup portion and a lid portion coupled to the cup portion. The lid portion includes a drinking spout having apertures. The detachable handle includes a ring portion that engages the lid and/or the cup portion, and a pair of grasping portions that extend axially and radially away from the ring portion. Hook portions are radially aligned with, and extend axially opposite the grasping portions, and are engageable with an upper surface of the lid portion. Moving the grasping portions radially inwardly causes the hook portions to move radially outwardly for disengagement from the upper surface and removal of the handle from the sippy cup.

US Patent:

20130061455, Mar 14, 2013

Filed:

Sep 9, 2011

Appl. No.:

13/229028

Inventors:

Brian William Greene - Roslindale MA, US

International Classification:

B23P 17/00

US Classification:

29592

Abstract:

The present embodiment provides an algae bioreactor comprising a coaxial configuration for the optimal dispersion of light and gas.

US Patent:

20130099313, Apr 25, 2013

Filed:

Oct 19, 2011

Appl. No.:

13/276395

Inventors:

Eduard A. CARTIER - New York NY, US
Brian J. GREENE - Wappingers Falls NY, US
Dechao GUO - Fishkill NY, US
Gan WANG - Fishkill NY, US
Yanfeng WANG - Fishkill NY, US
Keith Kwong Hon WONG - Wappingers Falls NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H01L 29/78
H01L 21/28

US Classification:

257347, 438595, 257E29255, 257E21158

Abstract:

FinFET structures and methods of manufacturing the FinFET structures are disclosed. The method includes performing an oxygen anneal process on a gate stack of a FinFET structure to induce Vt shift. The oxygen anneal process is performed after sidewall pull down and post silicide.

US Patent:

20130168804, Jul 4, 2013

Filed:

Feb 27, 2013

Appl. No.:

13/778419

Inventors:

International Business Machines Corporation - Armonk NY, US
Brian J. Greene - Fishkill NY, US
Dureseti Chidambarrao - Weston CT, US
Gregory G. Freeman - Wappinger Falls NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H01L 29/06
H01L 21/762

US Classification:

257510, 438435

Abstract:

A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region.

US Patent:

6796250, Sep 28, 2004

Filed:

Feb 13, 2003

Appl. No.:

10/366290

Inventors:

Brian W. Greene - Quincy MA 02169

International Classification:

F23B 700

US Classification:

110233, 110238

Abstract:

A waste water recovery and utilization system that converts waste water including gray water, liquid sewerage waste and solid macerated sewerage waste to steam and to electricity comprises a gray water tank, a sewerage tank, a steam generator with a gray water crucible for vaporizing the gray water and a sewerage crucible for vaporizing the liquid sewerage waste and for incinerating the solid macerated sewerage waste thereby generating steam for space heating. A variable speed injection pump cooperates with the gray water tank, with the sewerage tank, with the gray water crucible and with the sewerage crucible. Condensate is collected in a condensate tank. The system is operable on multiple fuels, including hydrogen and oxygen provided by the system, natural gas and liquid propane gas. Alternate energy including solar, wind and mechanical, supply electrical power to an electrolysis machine when conventional electrical energy is to be conserved.