Brian A Kelley

US Patent:

61987794, Mar 6, 2001

Filed:

May 5, 1999

Appl. No.:

9/305701

Inventors:

David B. Taubenheim - Boynton Beach FL
Brian T. Kelley - Delray Beach FL
David M. Johnson - Delray Beach FL

Assignee:

Motorola - Schaumburg IL

International Classification:

H03K 900

US Classification:

375316

Abstract:

A radio receiver circuit (200) is used for receiving a multi-level signal (201) that includes a plurality of symbols, wherein each level is representative of a symbol of data. Baseband samples are generated for each symbol, whereby each baseband sample has a phase and a signal level. The radio receiver circuit (200) measures the received signal environment. A digital circuit (212) selects a scan duration from a scan duration table (251) based on the measured signal environment and a combination of signal types used for classification of the received signal. The digital circuit tallies, by category, occurrences of the baseband samples, whereby each category is representative of one of a plurality of phases, and one of a plurality of signal level ranges. The digital circuit (212) selects a set of optimized thresholds from a table of predetermined, optimized thresholds (252), based on the measured signal environment and a combination of signal types, and correlates the tallies to at least one template, and classifies the multi-level signal according to the correlation results and the selected optimized thresholds.

US Patent:

58479813, Dec 8, 1998

Filed:

Sep 4, 1997

Appl. No.:

8/923329

Inventors:

Brian Todd Kelley - Delray Beach FL
David Mark Johnson - Delray Beach FL

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 752

US Classification:

3647505

Abstract:

A multiply accumulate circuit (600) includes a multiply accumulate reduction circuit (527) that generates P current accumulated operands during an iteration. P operand registers (582) are coupled to the multiply accumulate reduction circuit (527). A corresponding one of the P current accumulated operands is stored in each of the P operand registers (582) in place of one of the P partial accumulated operands in response to the iteration. Each of P feedback paths (593) couples one of P outputs of the P operand registers (582) to a corresponding one of P feedback inputs of the multiply accumulate reduction circuit (527). An adder (561) that is coupled to the P outputs through isolation circuits (570) generates an output (551) in N iterations that is a sum of N products, each being a product of one of a series of N multipliers and one of a series of N multiplicands.

US Patent:

61920894, Feb 20, 2001

Filed:

Aug 7, 1998

Appl. No.:

9/130930

Inventors:

Jose G. Corleto - Lake Worth FL
Brian Todd Kelley - Delray Beach FL
Shareq Rahman - Avenel NJ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H04L 2706

US Classification:

375344

Abstract:

An automatic frequency control circuit (84) and a method for automatic frequency control in a digital receiver includes a CORDIC vector rotation processor (88), an FM demodulator (100) and an integrator (72). The circuit and method utilize the CORDIC computing technique to simplify required circuitry and to reduce required software processing power over conventional automatic frequency control techniques.

US Patent:

62332872, May 15, 2001

Filed:

Apr 4, 1997

Appl. No.:

8/825984

Inventors:

Brian Todd Kelley - Delray Beach FL
Luis Augusto Bonet - Southlake TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03D 104
H03M 302

US Classification:

375316

Abstract:

A mixer (200, 201) including a transformation circuit (210) is used for frequency converting a first digital signal (208), sampled at a first sampling rate and operating at a first frequency, to a second digital signal (214) operating at a desired frequency. The transformation circuit (210) is adapted to modify and filter the first digital signal (208) to eliminate unwanted frequencies in the first digital signal (208) and to alter the first sampling rate of the first digital signal (208) by a predetermined factor to generate a modified and filtered first digital signal (308) operating at a second sampling rate and the first frequency. The transformation circuit (210) is further adapted to mix the modified and filtered first digital signal (308) with a predetermined injection signal (312) to generate the second digital signal (214) operating at the desired frequency and the second sampling rate.

US Patent:

56596952, Aug 19, 1997

Filed:

Jun 2, 1995

Appl. No.:

8/459859

Inventors:

Brian T. Kelley - Boynton Beach FL
Tan Nhat Dao - Austin TX
Duncan Fisher - Mission Viejo CA

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 1206

US Classification:

395405

Abstract:

A method and apparatus for an improving memory access bandwidth that can be used in a digital signal processor (DSP) (500) is accomplished by modifying addresses (302, 304) generated by an address generation unit (AGU) (102) of the DSP (500). Two addresses (302, 304) are generated by the AGU (102). One of the two addresses (302) is used to address two parallel memory blocks (308, 310) in a single memory simultaneously, and the other address (304) is modified by a modulo increment function to produce two additional addresses (404, 406) that also address the parallel memory blocks (308, 310). With such a method and apparatus, four simultaneous memory reads can occur, effectively doubling the memory access bandwidth in the DSP system (500) without modification of the AGU (102) or program controller (510).