Brian K Kirkland

US Patent:

61811211, Jan 30, 2001

Filed:

Mar 4, 1999

Appl. No.:

9/262430

Inventors:

Brian Kirkland - Austin TX
Steven Meyers - Round Rock TX
Bertrand J. Williams - Austin TX

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

G05F 320

US Classification:

323313

Abstract:

An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a first current in response to a reference voltage. The first current may vary as a function of temperature. The second circuit may be configured to generate a second current to counteract for the variations of the first current. The second current may vary as a function of temperature. The third circuit may be configured to generate a third current in response to the first current and the second current.

US Patent:

57511799, May 12, 1998

Filed:

Apr 26, 1996

Appl. No.:

8/639369

Inventors:

David Michael Pietruszynski - Austin TX
James Dub Austin - Austin TX
Brian Kirkland - Austin TX

Assignee:

Crystal Semiconductor - Austin TX

International Classification:

H03K 1716

US Classification:

327379

Abstract:

An output driver is provided for operating in a primary power supply environment to drive an output system that can have voltages associated therewith that are higher than the primary power supply level. The driver includes a pull-down N-channel (34) and a pull-up P-channel transistor (44). An output node (40) is driven by the transistor (34) and (44). An N-channel protection device (38) is disposed between node (40) and transistor (34) and an N-channel transistor (48) is disposed between node (40) and transistor (44). Transistor (38) has the gate thereof biased to the primary supply voltage level and the transistor (48) has the gate thereof biased to a voltage slightly above the primary supply voltage level. This configuration allows a common control signal varying up to the primary power supply level utilized to drive both transistors (34) and (44) and also to remove the requirement that any of the wells associated with the driver transistors be biased to a voltage above the primary supply voltage level, to prevent current being conducted to the primary supply from the output node during a high voltage condition or for the voltage of any of the transistors to exceed a voltage slightly above that of the primary voltage supply level.

US Patent:

62293451, May 8, 2001

Filed:

Sep 15, 1999

Appl. No.:

9/396344

Inventors:

Brian Kirkland - Austin TX
Nathan Y. Moyal - Austin TX

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

H03K 522

US Classification:

327 65

Abstract:

An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a first current in response to a first input signal. The second circuit may be configured to generate a second current in response to a second input signal. The third circuit may be configured to present a first pulse of current at a first output or a second pulse of current at a second output in response to the first and second currents.

US Patent:

62081934, Mar 27, 2001

Filed:

Jan 15, 1999

Appl. No.:

9/232344

Inventors:

Nathan Y. Moyal - Austin TX
Brian G. Kirkland - Austin TX

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

H03K17/62

US Classification:

327411

Abstract:

A circuit comprising a plurality of input devices, a plurality of de-select devices and a selector device. The plurality of input devices may each be configured to receive an input signal. The plurality of de-select devices may each be configured to present an output in response (i) one of the plurality of inputs and (ii) one of a plurality of de-select signals. The selector device may be configured to present the plurality of de-select signals. In general, all but one of the de-select signals is active at a time.