Brian E Longhenry

US Patent:

7120811, Oct 10, 2006

Filed:

Aug 29, 2002

Appl. No.:

10/230715

Inventors:

Ravi B. Bingi - Austin TX, US
John Dambik - Austin TX, US
Brian E. Longhenry - Austin TX, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1/32
G11C 11/4074
G06F 11/30

US Classification:

713324, 713300, 713340

Abstract:

Power control signals for main power and RAM power are utilized to determine when the system is in the suspend to RAM state. Once the system is determined to be in the suspend to RAM state state, a control circuit detects peripheral activity, such as activity of a mouse or a keyboard, and generate a wake-up signal.

US Patent:

20080114918, May 15, 2008

Filed:

Nov 9, 2006

Appl. No.:

11/595637

Inventors:

Ravi B. Bingi - Austin TX, US
Ranger H. Lam - Austin TX, US
Thomas Madaelil - Austin TX, US
Lloyd W. Gauthier - Austin TX, US
Brian E. Longhenry - Austin TX, US
Kristy M. Cates - Austin TX, US
Christopher E. Tressler - Austin TX, US

International Classification:

G06F 13/00

US Classification:

710300

Abstract:

A method for providing multiple configurations for a computer system. The method provides interconnection of processor boards in a first configuration and a second configuration. In the first configuration, a first plurality of processor boards are interconnected through a first backplane. In a second configuration, a second plurality of processor boards are interconnected through a second backplane. The first and second pluralities of processor boards are interchangeable with each other.

US Patent:

20120258611, Oct 11, 2012

Filed:

Apr 5, 2011

Appl. No.:

13/079912

Inventors:

Ravi B. Bingi - Austin TX, US
Ranger H. Lam - Austin TX, US
Jason R. Talbert - Austin TX, US
Pravind K. Hurry - Austin TX, US
Brian E. Longhenry - Austin TX, US
Andrew W. Steinbach - Austin TX, US
Jeff H. Gruger - Austin TX, US

International Classification:

H05K 1/02
H05K 1/00
H05K 3/00
H01R 12/00

US Classification:

439 55, 174250, 174261, 29829

Abstract:

An apparatus includes a printed circuit board including a connector footprint comprising a first footprint portion operative to receive a first connector portion and a second footprint portion operative to receive a second connector portion. The first footprint portion is compliant with a first communications link type and the first and second footprint portions are jointly compliant with a second communications link type. The printed circuit board includes first conductive traces coupled to the first footprint portion and a first device footprint. The first conductive traces are selectively configurable according to a selected one of the first and second communications link types. The printed circuit board includes a second conductive traces coupled to the second footprint portion and the first device footprint. In at least one embodiment of the apparatus, the first communications link type is AC-coupled and the second communications link type is DC-coupled.

US Patent:

60095059, Dec 28, 1999

Filed:

Dec 2, 1996

Appl. No.:

8/759046

Inventors:

John S. Thayer - Houston TX
Gary W. Thome - Tomball TX
Brian E. Longhenry - Cypress TX
John G. Favor - Scotts Valley CA
Frederick D. Weber - San Jose CA

Assignee:

Compaq Computer Corp. - Houston TX
Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1716

US Classification:

712 6

Abstract:

A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands. In one embodiment, multiple ALUs may each receive one operand from a fixed source register slot location, where the fixed slot location may be different for each ALU.

US Patent:

62155040, Apr 10, 2001

Filed:

Aug 1, 1997

Appl. No.:

8/905685

Inventors:

Brian E. Longhenry - Cypress TX
Gary W. Thome - Tomball TX
John S. Thayer - Houston TX

Assignee:

Compaq Computer Corporation - Houston TX

International Classification:

G06T 1120

US Classification:

345443

Abstract:

A routable operand and selectable operation processor multimedia extension unit is employed to draw lines in a video system using an efficient, parallel technique. A first series of integral y pixel values and error values are calculated according to Bresenham's line drawing algorithm. Then, subsequent pixels and error values are calculated in parallel based on the previously calculated values.

US Patent:

58931457, Apr 6, 1999

Filed:

Dec 2, 1996

Appl. No.:

8/757115

Inventors:

John S. Thayer - Houston TX
Gary W. Thome - Tomball TX
Brian E. Longhenry - Cypress TX

Assignee:

Compaq Computer Corp.
Advanced Micro Devices, Inc.

International Classification:

G06F 1200

US Classification:

711125

Abstract:

A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands.

US Patent:

59918659, Nov 23, 1999

Filed:

Dec 31, 1996

Appl. No.:

8/774745

Inventors:

Brian E. Longhenry - Cypress TX
Gary W. Thome - Tomball TX
John S. Thayer - Houston TX

Assignee:

Compaq Computer Corporation - Houston TX

International Classification:

G06F 1300

US Classification:

712 7

Abstract:

A routable operand and selectable operation processor multimedia extension unit is employed to motion compensate MPEG video using improved vector processing. A vector processing unit executes an add and divide instruction that adds two vector registers and divides the result in a single instruction. This is implemented through loading a first vector register with a first plurality of elements from a source block. A second vector register is then loaded with a second plurality of elements that are adjacent to the first plurality of elements. The add and divide instruction is then executed on the first and second vector registers, yielding an interpolated source element that is stored in a resultant vector register.

US Patent:

6047372, Apr 4, 2000

Filed:

Apr 13, 1999

Appl. No.:

9/290837

Inventors:

John S. Thayer - Houston TX
Brian E. Longhenry - Cypress TX
John G. Favor - Scotts Valley CA
Frederick D. Weber - San Jose CA

Assignee:

Compaq Computer Corp. - Houston TX
Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 700

US Classification:

712222

Abstract:

A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands. In one embodiment multiple ALUs may each receive one operand from a fixed source register slot location, where the fixed slot location may be different for each ALU.