Brian Edward Marchant

US Patent:

20010025340, Sep 27, 2001

Filed:

Mar 30, 2001

Appl. No.:

09/822212

Inventors:

Brian Marchant - Woodside CA, US

International Classification:

H04K001/00
H04L009/00

US Classification:

713/150000, 380/028000

Abstract:

A data encryption/decryption apparatus is disclosed which includes a controller coupled to an array of random data, an encryptor/decryptor and a plurality of encryption/decryption algorithms. The array of random data and the plurality of encryption/decryption algorithms are stored on an electronically readable media. The data encryption/decryption apparatus can encrypt and decrypt data, video, audio. The electronically readable media includes random access memory, read only memory, magnetic media, optical media, magneto-optical media, CDROM, digital video disk (DVD), hard disk, a remote computer memory storage location accessible via an electronic network such as a telephone system or a computer network, or any other electronically readable media method. The controller is responsive to a key code input to the controller. The controller determines a first computed address in the array of random data and a control data length. The controller then retrieves the control data from the first computed address in the array of random data.

US Patent:

62160516, Apr 10, 2001

Filed:

May 4, 1998

Appl. No.:

9/072201

Inventors:

Arthur L. Hager - Auburn CA
Brian E. Marchant - Woodside CA
Shouping Chuang - Carmichael CA
Ki Duk Kim - Orangevale CA

Assignee:

NEC Electronics, Inc. - Santa Clara CA

International Classification:

G05B 902
G06F 1900
H02H 305

US Classification:

700 82

Abstract:

A manufacturing system is disclosed which includes first and second control devices as well as a communication terminal which controls communication with the control devices. The communications terminal includes an interceptor module which receives information from the manufacturing device and provides this information to the first and second control devices.

US Patent:

62401831, May 29, 2001

Filed:

Oct 15, 1999

Appl. No.:

9/419337

Inventors:

Brian E. Marchant - Woodside CA

International Classification:

H04L 900

US Classification:

380 28

Abstract:

A data encryption/decryption apparatus is disclosed which includes a controller coupled to an array of random data, an encryptor/decryptor and a plurality of encryption/decryption algorithms. The array of random data and the plurality of encryption/decryption algorithms are stored on an electronically readable media. The data encryption/decryption apparatus can encrypt and decrypt data, video, audio. The electronically readable media includes random access memory, read only memory, magnetic media, optical media, magneto-optical media, CDROM, digital video disk (DVD), hard disk, a remote computer memory storage location accessible via an electronic network such as a telephone system or a computer network, or any other electronically readable media method. The controller is responsive to a key code input to the controller. The controller determines a first computed address in the array of random data and a control data length.

US Patent:

62367285, May 22, 2001

Filed:

Oct 12, 1999

Appl. No.:

9/416966

Inventors:

Brian E. Marchant - Woodside CA

International Classification:

H04L 900

US Classification:

380 28

Abstract:

A security apparatus including a number input device (302), an address register (312) responsive to the number input device, an encryption schema memory (316) addressable by the address register to produce an output code and a relative address code, and address incrementing logic (310) responsive the relative address code and operative to increment the address register. The apparatus also preferably includes a PIN register (304) coupled to the number input device, a public code register (306) coupled to the number input device, and merging logic (308) merging outputs of the PIN register and the public code register to be input to the address register. The apparatus also preferably includes an output shift register operative to shift out the output code of the encryption schema memory. The encryption schema memory can be read only memory, writeable memory, or both.

US Patent:

58646540, Jan 26, 1999

Filed:

Feb 19, 1997

Appl. No.:

8/801237

Inventors:

Brian E. Marchant - Woodside CA

Assignee:

NEC Electronics, Inc. - Santa Clara CA

International Classification:

G06F 1300

US Classification:

39518201

Abstract:

A fault-tolerant management information system includes three or more data management systems (e. g. data base systems) that replicate data. Data access requests resulting from user requests to application systems are issued by user request processing entities and forwarded by interceptors to all the data management systems. Responses from the data management systems are obtained, and a maximum group of identical responses provides the correct response, even in the case of "soft" errors not flagged by error codes. Errors are reported to an administration system, and correction of the data base containing the errors is handled by a recovery server. Overall system performance is further enhanced by including data base query systems, which replicate the data. Data access requests resulting from data base query requests are issued by query systems to the data base query systems.

US Patent:

60944862, Jul 25, 2000

Filed:

Jul 23, 1999

Appl. No.:

9/359857

Inventors:

Brian E. Marchant - Woodside CA

International Classification:

H04L 900

US Classification:

380 52

Abstract:

A security apparatus including a number input device (302), an address register (312) responsive to the number input device, an encryption schema memory (316) addressable by the address register to produce an output code and a relative address code, and address incrementing logic (310) responsive the relative address code and operative to increment the address register. The apparatus also preferably includes a PIN register (304) coupled to the number input device, a public code register (306) coupled to the number input device, and merging logic (308) merging outputs of the PIN register and the public code register to be input to the address register. The apparatus also preferably includes an output shift register operative to shift out the output code of the encryption schema memory. The encryption schema memory can be read only memory, writeable memory, or both.

US Patent:

57484708, May 5, 1998

Filed:

Feb 5, 1996

Appl. No.:

8/596785

Inventors:

Arthur L. Hager - Auburn CA
Brian E. Marchant - Woodside CA
Shouping Chuang - Carmichael CA
Ki Duk Kim - Orangeville CA

Assignee:

NEC Electronics, Inc. - Santa Clara CA

International Classification:

G05B 902

US Classification:

364187

Abstract:

A manufacturing system is disclosed which includes first and second control devices as well as a communication terminal which controls communication with the control devices. The communications terminal includes an interceptor module which receives information from the manufacturing device and provides this information to the first and second control devices.