Byungha Ha Joo from 367 Seaton Dr, Folsom, CA 95630, age 59, Phone: (916)9851166

Shallow Trench Avoidance In Integrated Circuits
view source
US Patent:

7475381, Jan 6, 2009
Filed:

Mar 30, 2006
Appl. No.:

11/394621
Inventors:

Jeffrey B. Davis - El Dorado Hills CA, US
Rajashri Doddamani - Folsom CA, US
Byungha Joo - San Jose CA, US
Duc G. Nguyen - El Dorado Hills CA, US
Darshana Surti - Roseville CA, US
Eva Yim - Folsom CA, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G06F 17/50
US Classification:

716 19, 716 1, 716 2
Abstract:

Diffusion regions in a standard cell design are bridged across cell boundaries. Shallow trench isolation is reduced and nitride passivation thickness variation is reduced.

Low Power Dual Trip Point Input Buffer Circuit
view source
US Patent:

6566910, May 20, 2003
Filed:

Dec 19, 2001
Appl. No.:

10/034080
Inventors:

Byungha Joo - San Jose CA
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

H03K 3037
US Classification:

326 83, 326 57, 327206
Abstract:

A method and system for reducing the power consumption in a class of circuits utilizing inverters which rely upon a resistive load design such as pseudo NMOS and/or pseudo PMOS. In particular, rather than utilizing the load network to provide a resistive load, which imposes static dissipation, the load network is driven by the input signal along with the logic network. The circuit is then configured to function in a CMOS configuration by driving both the load and logic networks with the input signal.

Method And System For Building A Cell Library With Segmented Timing Arc Delay Model
view source
US Patent:

20180137225, May 17, 2018
Filed:

Nov 15, 2016
Appl. No.:

15/351771
Inventors:

Byungha Joo - San Jose CA, US
International Classification:

G06F 17/50
Abstract:

Multiple timing arc gate delay modelling method is described. Propagation delay can be divided into several timing arcs at circuit threshold voltage. Additionally, each timing arc can be modelled as a function of actual source of driving force. The logic threshold voltage of the functional gates is one single voltage level, which is usually half of the supplied voltage. Therefore, the RC tree model which is extracted from the wires is still valid. In this way, precise voltage based delay calculation is accomplished while maintaining the same interfacing method with passive RC elements from wirings.