Carl H Gray

US Patent:

7770078, Aug 3, 2010

Filed:

May 23, 2008

Appl. No.:

12/153795

Inventors:

Jason Thurston - Raleigh NC, US
Carl Thomas Gray - Apex NC, US

Assignee:

ARM Limited - Cambridge

International Classification:

G01R 31/28

US Classification:

714715, 714733

Abstract:

An integrated circuit includes a plurality of serial data transmitters and a plurality of serial data receivers. On-chip test signal paths with associated on-chip test circuits are provided so as to permit on-chip serial data communication to be performed with test characteristics imposed by the on-chip test circuits thereby providing on-chip stress testing of the data transmitter and the serial data receiver.

US Patent:

8179952, May 15, 2012

Filed:

May 23, 2008

Appl. No.:

12/153796

Inventors:

Jason Thurston - Raleigh NC, US
Carl Thomas Gray - Apex NC, US

Assignee:

Integrated Device Technology inc. - San Jose CA

International Classification:

H04B 3/46

US Classification:

375224, 375221, 375219, 375226, 375227

Abstract:

An integrated circuit is provided comprising: a serial transmitter, a serial receiver and a serial connection providing communication between the serial transmitter and the serial receiver. The integrated circuit further comprises a duty cycle distortion circuit so that the integrated circuit can be stress tested by distorting the duty cycle of a signal within the integrated circuit.

US Patent:

8427195, Apr 23, 2013

Filed:

May 10, 2012

Appl. No.:

13/468668

Inventors:

Seong Kwan Lee - Suwon-si, KR
Hyun Woo Choi - Atlanta GA, US
Sung Yeol Kim - Yogin-si, KR
David Keezer - Atlanta GA, US
Carl Gray - Atlanta GA, US
Te-Hui Chen - Atlanta GA, US

Assignee:

Samsung Electronics Co., Ltd. - Gyeonggi-Do
Georgia Tech Research Corporation - Atlanta GA

International Classification:

H03K 19/00

US Classification:

326 16, 326 52, 324 731, 714738

Abstract:

A digital signal generator includes an input unit configured to receive signal information of a target data signal, a controller configured to calculate at least two delay values and at least two data values, the at least two delay values and the at least two data values being used to generate a data signal corresponding to the signal information input through the input unit, a multi-phase clock generator configured to delay a reference clock signal based on the at least two delay values to generate at least two clock signals having different phases, a signal generator configured to generate at least two data signals by assigning the at least two data values to the at least two clock signals, and a logic gate unit configured to generate the data signal corresponding to the signal information input through the input unit based on the at least two data signals.

US Patent:

20090290624, Nov 26, 2009

Filed:

May 23, 2008

Appl. No.:

12/153801

Inventors:

Jason Thurston - Raleigh NC, US
Carl Thomas Gray - Apex NC, US
Terry Perkinson - Cary NC, US

Assignee:

ARM Limited - Cambridge

International Classification:

H04B 1/38

US Classification:

375221

Abstract:

The present invention provides an integrated circuit comprising a serial transmitter, a serial receiver and a serial connection providing communication between the serial transmitter and the serial receiver. The serial transmitter comprises a clock generator and a serializer for serializing data to be transmitted to the serial receiver. A clock control unit coupled to the clock generator alters the clock phase of the clock signal to stress test the serial receiver.

US Patent:

20090292962, Nov 26, 2009

Filed:

May 23, 2008

Appl. No.:

12/153794

Inventors:

Jason Thurston - Raleigh NC, US
Carl Thomas Gray - Apex NC, US

Assignee:

ARM Limited - Cambridge

International Classification:

G01R 31/3183
G06F 11/263

US Classification:

714716, 714E11177

Abstract:

An integrated circuit having a data receiver circuit for a serial data signal also includes a test data generating circuit for self-test purposes. The test generating circuit includes a filter circuit which processes an input test serial data signal to generate an output test serial data signal having enhanced inter-symbol interference for loopback to the data receiver circuit so as to test that data receiver circuit.

US Patent:

52296687, Jul 20, 1993

Filed:

Mar 25, 1992

Appl. No.:

7/857457

Inventors:

Thomas A. Hughes - Raleigh NC
Carl T. Gray - Cary NC
Wentai Liu - Cary NC
Ralph K. Cavin - Cary NC

Assignee:

North Carolina State University of Raleigh - Raleigh NC

International Classification:

H03K 513
H03K 5159

US Classification:

307605

Abstract:

A data signal may be sampled at high speed using a clock signal by propagating the data signal and the clock signal through a series of data and clock delay elements, respectively, and latching the corresponding delayed data and clock signals. The sampling speed is thereby controlled by the relative skew between the clock and data signals, which can be made relatively small and may be limited only by noise and random variations in fabrication. Accordingly, high speed sampling may be obtained.

US Patent:

62223801, Apr 24, 2001

Filed:

Jun 11, 1999

Appl. No.:

9/330968

Inventors:

Robert Glen Gerowitz - Raleigh NC
Carl Thomas Gray - Apex NC
John Marshall - Cary NC
Christopher G. Riedle - Apex NC
Raymond Paul Rizzo - Hillsborough NC

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 19173

US Classification:

326 38

Abstract:

An interface system that conveys data at approximately 500 MBitsps between modules. The interface system performs multistream serialization at the transmitter and multistream de-serialization at the Receiver. As a consequence, fewer interface connections are required between the modules.