Carlos Esteban Chacon

US Patent:

6391668, May 21, 2002

Filed:

May 1, 2000

Appl. No.:

09/562346

Inventors:

Carlos M. Chacon - Orlando FL
Sundar S. Chetlur - Orlando FL
Brian E. Harding - Orlando FL
Minesh A. Patel - Orlando FL
Pradip K. Roy - Orlando FL

Assignee:

Agere Systems Guardian Corp. - Orlando FL

International Classification:

H01L 2166

US Classification:

438 17, 438197, 324769

Abstract:

The present invention provides a method of determining a trap density of a semiconductor substrate/dielectric interface. In one embodiment, the method comprises measuring a current within a semiconductor substrate resulting from a flow of carriers from traps located near the interface, wherein the measured current is a function of the number of traps located at the interface, and determining the trap density as a function of the measured current.

US Patent:

6548422, Apr 15, 2003

Filed:

Sep 27, 2001

Appl. No.:

09/966779

Inventors:

Pradip K. Roy - Orlando FL
David C. Brady - Windermere FL
Carlos M. Chacon - Orlando FL

Assignee:

Agere Systems, Inc. - Allentown PA

International Classification:

H01L 2348

US Classification:

438775, 438770, 438287

Abstract:

A transistor gate dielectric structure includes an oxide layer formed on a substrate, a superjacent nitride layer and a transition layer interposed therebetween. The presence of the transition layer alleviates stress between the nitride and oxide layers and minimizes any charge trapping sites between the nitride and oxide layers. The transition layer includes both nitrogen and oxygen as components. The method for forming the structure includes forming the transition layer using a remote nitridation reactor at a sufficiently low temperature such that virtually no nitrogen reaches the interface formed between the oxide layer and the substrate. The oxide layer/substrate interface is relatively pristine and defect-free. In an exemplary embodiment, the oxide layer may be a graded structure formed using two distinct processing operations, a first operation at a relatively low temperature and a final operation at a temperature above the viscoelastic temperature of the oxide film.

US Patent:

6664800, Dec 16, 2003

Filed:

Jan 8, 2001

Appl. No.:

09/756965

Inventors:

Carlos M. Chacon - Orlando FL
Sundar Chetlur - Singapore, SG
Pradip K. Roy - Orlando FL

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

G01R 3100

US Classification:

324765, 324750

Abstract:

A non-contact method for determining a quality of a semiconductor dielectric. The method includes depositing a charge on a dielectric to achieve a high voltage on the dielectric, measuring a voltage drop of the dielectric as a function of time, and determining a soft breakdown voltage of the dielectric from the voltage drop as a function of time. The amount of charge that is deposited may vary. For example, the charge may be deposited until a voltage that ranges from about 4 megavolts to about 16 megavolts is achieved on the dielectric. The amount of charge may also depend on the thickness of the dielectric. For example, applying a charge as a function of the thickness may include applying 4 megavolts when the thickness is about 1. 2 nm or applying 16 megavolts when the thickness is about 5. 0 nm.

US Patent:

20030186499, Oct 2, 2003

Filed:

Mar 24, 2003

Appl. No.:

10/396591

Inventors:

Pradip Roy - Orlando FL, US
David Brady - Windermere FL, US
Carlos Chacon - Orlando FL, US

Assignee:

Agere Systems Inc.

International Classification:

H01L021/8238

US Classification:

438/200000

Abstract:

A transistor gate dielectric structure includes an oxide layer formed on a substrate, a superjacent nitride layer and a transition layer interposed therebetween. The presence of the transition layer alleviates stress between the nitride and oxide layers and minimizes any charge trapping sites between the nitride and oxide layers. The transition layer includes both nitrogen and oxygen as components. The method for forming the structure includes forming the transition layer using a remote nitridation reactor at a sufficiently low temperature such that virtually no nitrogen reaches the interface formed between the oxide layer and the substrate. The oxide layer/substrate interface is relatively pristine and defect-free. In an exemplary embodiment, the oxide layer may be a graded structure formed using two distinct processing operations, a first operation at a relatively low temperature and a final operation at a temperature above the viscoelastic temperature of the oxide film.

US Patent:

62516973, Jun 26, 2001

Filed:

Oct 6, 2000

Appl. No.:

9/684015

Inventors:

Carlos M. Chacon - Orlando FL
Pradip K. Roy - Orlando FL

Assignee:

Agere Systems Guardian Corp. - Orlando FL

International Classification:

H01L 2166

US Classification:

438 17

Abstract:

The present invention provides a method for controlling a process parameter for fabricating a semiconductor wafer. In one embodiment, the method includes forming a test substrate using a given process parameter, determining a flatband voltage of the test substrate, and modifying the given process parameter to cause the flatband voltage to approach zero. The process parameter that is modified to cause the flatband voltage to approach zero may vary. The flatband may be determined by a non-contact method, which uses a kelvin probe to measure the flatband voltage and a corona source to deposit a charge on the test substrate.

US Patent:

62658905, Jul 24, 2001

Filed:

Aug 26, 1999

Appl. No.:

9/383457

Inventors:

Carlos M. Chacon - Orlando FL
Sailesh Chittipeddi - Allentown PA
Pradip K. Roy - Orlando FL

Assignee:

Lucent Technologies Inc. - Murray Hill NJ

International Classification:

G01R 3102

US Classification:

324765

Abstract:

A method and apparatus for in-line, non-contact depletion capacitance measurement of a semiconductor wafer using non-contact voltage measurement and non-contact surface photovoltage response.

US Patent:

62551280, Jul 3, 2001

Filed:

Aug 6, 1998

Appl. No.:

9/130240

Inventors:

Carlos M. Chacon - Orlando FL
Pradip K. Roy - Orlando FL

Assignee:

Lucent Technologies Inc. - Murray Hill NJ

International Classification:

B01R 3126

US Classification:

438 17

Abstract:

The present invention provides a non-contact method for determining whether a contaminant is present in a semiconductor wafer having a substrate/dielectric interface formed thereon. in one advantageous embodiment, the method comprises field inducing a junction in equilibrium inversion in the semiconductor wafer device. A conventional corona source may be used to induce the junction to equilibrium inversion. This particular embodiment further includes forming a contaminant junction near the substrate/dielectric interface when the contaminant is present in the semiconductor wafer by adding charge and pulsing the junction out of equilibrium. A surface voltage measurement, which may be taken with a Kelvin probe, is obtained by measuring a change in a surface voltage as a function of time. The method further includes determining whether the contaminant is present in the semiconductor wafer from the change in the surface voltage. When the contaminant is present in the device, the change in the surface voltage is negligible.

US Patent:

62074687, Mar 27, 2001

Filed:

Oct 23, 1998

Appl. No.:

9/178317

Inventors:

Carlos M. Chacon - Orlando FL
Pradip K. Roy - Orlando FL

Assignee:

Lucent Technologies Inc. - Murray Hill NJ

International Classification:

H01L21/66
7
G01R31/26

US Classification:

438 17

Abstract:

The present invention provides a method for controlling a process parameter for fabricating a semiconductor wafer. In one embodiment, the method includes forming a test substrate using a given process parameter, determining a flatband voltage of the test substrate, and modifying the given process parameter to cause the flatband voltage to approach zero. The process parameter that is modified to cause the flatband voltage to approach zero may vary. The flatband may be determined by a non-contact method, which uses a kelvin probe to measure the flatband voltage and a corona source to deposit a charge on the test substrate.