Carlos J Fernandez

US Patent:

D648095, Nov 1, 2011

Filed:

Nov 11, 2010

Appl. No.:

29/378918

Inventors:

Carlos F. Fernandez - Miami Beach FL, US
Diego Lorenzo - Miami Beach FL, US

International Classification:

9900

US Classification:

D99 34

US Patent:

20150356498, Dec 10, 2015

Filed:

Jun 8, 2015

Appl. No.:

14/733113

Inventors:

Andres E. Casanova - AVENTURA FL, US
Carlos Damian Fernandez - Walnut CA, US

International Classification:

G06Q 10/08
G07B 15/06

Abstract:

Managing parking is carried out by associating an electronic tag with a vehicle, each tag configured to either receive, transmit, or both receive and transmit information at a low frequency using magnetic induction. A base station located in each parking space is likewise configured to either receive, transmit, or both receive and transmit information at a low frequency using magnetic induction. Either the tag or the base station will communicate identification information of both the tag and the base station to one or more servers, where parking can be managed. Communication with the server can be carried out in part using a publicly available radio frequency over a wide area network, such as one of the SigFox, LoRaWAN, or WEIGHTLESS protocols.

US Patent:

20150278005, Oct 1, 2015

Filed:

Jun 23, 2014

Appl. No.:

14/312327

Inventors:

- Armonk NY, US
Carlos A. Fernandez - Hialeah FL, US
Joab D. Henderson - Pflugerville TX, US
Jeffrey A. Sabrowski - Leander TX, US
Anuwat Saetow - Austin TX, US
Saravanan Sethuraman - Bangalore, IN

International Classification:

G06F 11/07

Abstract:

A method, system and computer program product are provided for implementing enhanced reliability of memory subsystems utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. The DRAM configuration includes a first buffer and a second buffer, each buffer including a validity counter. The validity counter for a receiving buffer is incremented as each respective data row from a transferring buffer is validated through Error Correction Code (ECC), Reliability, Availability, and Serviceability (RAS) logic and transferred to the receiving buffer, while the validity counter for the transferring buffer is decremented. Data are read from or written to either the first buffer or the second buffer based upon a respective count value of the validity counters.

US Patent:

20150278086, Oct 1, 2015

Filed:

Mar 27, 2014

Appl. No.:

14/227187

Inventors:

- Armonk NY, US
Carlos A. Fernandez - Hialeah FL, US
Joab D. Henderson - Pflugerville TX, US
Jeffrey A. Sabrowski - Leander TX, US
Anuwat Saetow - Austin TX, US
Saravanan Sethuraman - Bangalore, IN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/02
G06F 11/10

Abstract:

A method, system and computer program product are provided for implementing enhanced reliability of memory subsystems utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. The DRAM configuration includes a first buffer and a second buffer, each buffer including a validity counter. The validity counter for a receiving buffer is incremented as each respective data row from a transferring buffer is validated through Error Correction Code (ECC), Reliability, Availability, and Serviceability (RAS) logic and transferred to the receiving buffer, while the validity counter for the transferring buffer is decremented. Data are read from or written to either the first buffer or the second buffer based upon a respective count value of the validity counters.

US Patent:

20150213853, Jul 30, 2015

Filed:

Jan 30, 2014

Appl. No.:

14/168102

Inventors:

- ARMONK NY, US
Carlos A. Fernandez - Hialeah FL, US
Joab D. Henderson - Pflugerville TX, US
Jeffrey A. Sabrowski - Leander TX, US
Anuwat Saetow - Austin TX, US
Saravanan Sethuraman - Bangalore, IN

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY

International Classification:

G11C 7/10

Abstract:

A method, system and memory controller are provided for implementing simultaneous read and write operations in a memory subsystem utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. A DRAM includes a first partition and a second partition. A memory controller determines if memory requirements are above or below a usage threshold. If the memory requirements are below the usage threshold, the memory is partitioned into a read buffer and a write buffer, with writes going to the write buffer and reads coming from the read buffer, data being transferred from the write buffer to the read buffer through an Error Correction Code (ECC) engine. If the memory requirements are above the usage threshold, the entire memory is used for reads and writes.

US Patent:

20150213854, Jul 30, 2015

Filed:

Jun 20, 2014

Appl. No.:

14/310717

Inventors:

- Armonk NY, US
Carlos A. Fernandez - Hialeah FL, US
Joab D. Henderson - Pflugerville TX, US
Jeffrey A. Sabrowski - Leander TX, US
Anuwat Saetow - Austin TX, US
Saravanan Sethuraman - Bangalore, IN

International Classification:

G11C 7/10

Abstract:

A method, system and memory controller are provided for implementing simultaneous read and write operations in a memory subsystem utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. A DRAM includes a first partition and a second partition. A memory controller determines if memory requirements are above or below a usage threshold. If the memory requirements are below the usage threshold, the memory is partitioned into a read buffer and a write buffer, with writes going to the write buffer and reads coming from the read buffer, data being transferred from the write buffer to the read buffer through an Error Correction Code (ECC) engine. If the memory requirements are above the usage threshold, the entire memory is used for reads and writes.

US Patent:

20150127898, May 7, 2015

Filed:

Nov 7, 2013

Appl. No.:

14/074117

Inventors:

- Armonk NY, US
Carlos A. Fernandez - Hialeah FL, US
Joab D. Henderson - Pflugerville TX, US
William P. Hovis - Rochester MN, US
Jeffrey A. Sabrowski - Leander TX, US
Anuwat Saetow - Austin TX, US
Saravanan Sethuraman - Bangalore, IN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 11/406

US Classification:

711106

Abstract:

A refresh command is communicated to a memory device to initiate an interruptible refresh which contains multiple segment refreshes separated by interrupt boundaries. A command is communicated to the memory device before execution of a segment refresh and the segment refresh is delayed at an interrupt boundary. Alternatively, a first number of commands in a queue is determined. A first number of segment refreshes to execute is determined based on the first number of commands. The first number of segment refreshes to execute is communicated to the memory device to cause execution of the first number of segment refreshes. A second number of commands in the queue is determined. A second number of segment refreshes to execute is determined based on the second number of commands. The second number of segment refreshes to execute is communicated to the memory device to cause execution of the second number of segment refreshes.

US Patent:

20150127899, May 7, 2015

Filed:

Nov 7, 2013

Appl. No.:

14/074171

Inventors:

- Armonk NY, US
Carlos A. Fernandez - Hialeah FL, US
Joab D. Henderson - Pflugerville TX, US
William P. Hovis - Rochester MN, US
Jeffrey A. Sabrowski - Leander TX, US
Anuwat Saetow - Austin TX, US
Saravanan Sethuraman - Bangalore, IN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 11/406

US Classification:

711106

Abstract:

A refresh command is received from a memory controller. An interruptible refresh containing multiple segment refreshes is initiated. The segment refreshes are separated by interrupt boundaries. A command is received before execution of a segment refresh. The first command is executed and execution of the first segment refresh is delayed at a first interrupt boundary. Alternatively, a first number of segment refreshes to execute is received from a memory controller. The received first number of segment refreshes is executed. A second number of segment refreshes to execute is received from a memory controller. The received second number of segment refreshes is executed. No segment refreshes are executed between the execution of the first number of segment refreshes and the execution of the second number of segment refreshes.

Address:

13270 NW 8 St, Miami, FL 33182

Phone:

(305)2276860

VIN:

WBANU53539C118079

Make:

BMW

Model:

5 SERIES

Year:

2009

Address:

9760 SW 218 St, Cutler Bay, FL 33190

Phone:

(305)2548866

VIN:

1FMEU65E29UA44424

Make:

FORD

Model:

EXPLORER

Year:

2009

Address:

1365 Stillwater Dr, Miami Beach, FL 33141

VIN:

1G6DF577890170493

Make:

CADILLAC

Model:

CTS

Year:

2009

Address:

2245 SW 128 Ave, Miami, FL 33175

VIN:

1GTEC14C87Z563763

Make:

GMC

Model:

SIERRA 1500

Year:

2007

Address:

14021 SW 120 Ct, Miami, FL 33186

VIN:

1N6BD06T27C429676

Make:

NISSAN

Model:

FRONTIER

Year:

2007

Address:

2190 SW 17 St, Miami, FL 33145

VIN:

3TMJU62N67M037680

Make:

TOYOTA

Model:

TACOMA

Year:

2007

Address:

3311 SW 94 Ave, Miami, FL 33165

VIN:

5NPET46C87H238939

Make:

HYUNDAI

Model:

SONATA

Year:

2007

Address:

3020 SW 76 Ave, Miami, FL 33155

VIN:

JTDJT923875064209

Make:

TOYOTA

Model:

YARIS

Year:

2007