Babak Sadegh Sani

US Patent:

7982265, Jul 19, 2011

Filed:

Jan 22, 2008

Appl. No.:

12/018166

Inventors:

Ashok Challa - Sandy UT, US
Alan Elbanhawy - Hollister CA, US
Steven P. Sapp - Felton CA, US
Peter H. Wilson - Chandler AZ, US
Babak S. Sani - Oakland CA, US
Christopher B. Kocon - Mountain Top PA, US

Assignee:

Fairchild Semiconductor Corporation - San Jose CA

International Classification:

H01L 29/78

US Classification:

257341, 257331, 257E29067, 257E2926

Abstract:

A semiconductor power device includes a drift region of a first conductivity type, a well region extending above the drift region and having a second conductivity type opposite the first conductivity type, an active trench extending through the well region and into the drift region. The active trench, which includes sidewalls and bottom lined with dielectric material, is substantially filled with a first conductive layer and a second conductive layer. The second conductive layer forms a gate electrode and is disposed above the first conductive layer and is separated from the first conductive layer by an inter-electrode dielectric material. The device also includes source regions having the first conductivity type formed inside the well region and adjacent the active trench and a charge control trench that extends deeper into the drift region than the active trench and is substantially filled with material to allow for vertical charge control in the drift region. The charge control trench can be lined with a layer of dielectric material and substantially filled with conductive material. The active trench can include a second shield electrode made of conductive material disposed below the first shield electrode.

US Patent:

8143123, Mar 27, 2012

Filed:

Mar 3, 2008

Appl. No.:

12/041546

Inventors:

Thomas E. Grebs - Mountaintop PA, US
Rodney S. Ridley - Mountaintop PA, US
Steven P. Sapp - Felton PA, US
Peter H. Wilson - Wrightwood CA, US
Babak S. Sani - Oakland CA, US
Gary M. Dolny - Mountaintop PA, US
John Mytych - Mohnton PA, US
Becky Losee - Cedar Hills UT, US
Adam Selsley - Mountaintop PA, US
Christopher B. Kocon - Plains PA, US

Assignee:

Fairchild Semiconductor Corporation - South Portland ME

International Classification:

H01L 21/336

US Classification:

438259, 438283, 438270, 257E21019, 257341

Abstract:

A method for forming power semiconductor devices having an inter-electrode dielectric (IPD) layer inside a trench includes providing a semiconductor substrate with a trench, lining the sidewalls and bottom of the trench with a first layer of dielectric material, filling the trench with a first layer of conductive material to form a first electrode, recessing the first layer of dielectric material and the first layer of conductive material to a first depth inside the trench, forming a layer of polysilicon material on a top surface of the dielectric material and conductive material inside the trench, oxidizing the layer of polysilicon material, and forming a second electrode inside the trench atop the oxidized layer and isolated from trench sidewalls by a second dielectric layer. The oxidation step can be enhanced by either chemically or physically altering the top portion polysilicon such as by implanting impurities.

US Patent:

8143124, Mar 27, 2012

Filed:

Feb 15, 2008

Appl. No.:

12/032599

Inventors:

Ashok Challa - Sandy UT, US
Alan Elbanhawy - Hollister CA, US
Dean E. Probst - West Jordan UT, US
Steven P. Sapp - Felton CA, US
Peter H. Wilson - Wrightwood CA, US
Babak S. Sani - Oakland CA, US
Becky Losee - Cedar Hills UT, US
Robert Herrick - Lehi UT, US
James J. Murphy - South Jordan UT, US
Gordon K. Madson - Riverton UT, US
Bruce D. Marchant - Murray UT, US
Christopher B. Kocon - Plains PA, US
Debra S. Woolsey - Draper UT, US

Assignee:

Fairchild Semiconductor Corporation - South Portland ME

International Classification:

H01L 29/78
H01L 21/336

US Classification:

438270, 257341, 257E27091, 257E29201, 257E29257, 257E21655

Abstract:

A method of manufacturing a semiconductor device having a charge control trench and an active control trench with a thick oxide bottom includes forming a drift region, a well region extending above the drift region, an active trench extending through the well region and into the drift region, a charge control trench extending deeper into the drift region than the active trench, an oxide film that fills the active trench, the charge control trench and covers a top surface of the substrate, an electrode in the active trench, and source regions. The method also includes etching the oxide film off the top surface of the substrate and inside the active trench to leave a substantially flat layer of thick oxide having a target thickness at the bottom of the active trench.

US Patent:

20050167742, Aug 4, 2005

Filed:

Dec 29, 2004

Appl. No.:

11/026276

Inventors:

Ashok Challa - Sandy UT, US
Alan Elbanhawy - Hollister CA, US
Thomas Grebs - Mountaintop PA, US
Nathan Kraft - Pottsville PA, US
Dean Probst - West Jordan UT, US
Rodney Ridley - Mountaintop PA, US
Steven Sapp - Felton CA, US
Qi Wang - Sandy UT, US
Chongman Yun - Seoul City, KR
J.G. Lee - Puchon-Si, KR
Peter Wilson - Wrightwood CA, US
Joseph Yedinak - Mountaintop PA, US
J.Y. Jung - Kyunggi-do, KR
H.C. Jang - Kyoungki-do, KR
Babak Sani - Oakland CA, US
Richard Stokes - Shavertown PA, US
Gary Dolny - Mountaintop PA, US
John Mytych - Mohnton PA, US
Becky Losee - Cedar Hills UT, US
Adam Selsley - Mountaintop PA, US
Robert Herrick - Lehi UT, US
James Murphy - South Jordan UT, US
Gordon Madson - Riverton UT, US
Bruce Marchant - Murray UT, US
Christopher Rexer - Mountaintop PA, US
Christopher Kocon - Plains PA, US
Debra Woolsey - Draper UT, US

Assignee:

Fairchild Semiconductor Corp. - South Portland ME

International Classification:

G06F001/26

US Classification:

257328000

Abstract:

Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

US Patent:

20080197407, Aug 21, 2008

Filed:

Feb 28, 2008

Appl. No.:

12/039011

Inventors:

Ashok Challa - Sandy UT, US
Alan Elbanhawy - Hollister CA, US
Steven P. Sapp - Felton CA, US
Qi Wang - Sandy UT, US
Peter H. Wilson - Wrightwood CA, US
Babak S. Sani - Oakland CA, US
Christopher B. Kocon - Plains PA, US

International Classification:

H01L 29/78
H01L 21/20
H01L 21/336

US Classification:

257330, 438495, 438508, 438270, 257E29262, 257E2141, 257E2109

Abstract:

A method for controlling the thickness of an expitaxially grown semiconductor material includes providing a semiconductor substrate that is doped by dopants of a first type; forming a buffer layer atop the semiconductor substrate, the buffer layer being doped with dopants of a second type that has much less diffusivity relative to that of dopants of the first type and forming the expitaxially grown layer atop the buffer layer to a desired thickness. The buffer layer, which acts to counter an up-diffusion of the dopants of the first type from the substrate into the epitaxially grown layer, can be doped with arsenic or carbon or both arsenic and carbon. A semiconductor device includes the buffer layer to counter an up-diffusion of the dopants of the first type from the substrate into the epitaxially grown layer.

US Patent:

20120220091, Aug 30, 2012

Filed:

Mar 12, 2012

Appl. No.:

13/418128

Inventors:

Ashok Challa - Sandy UT, US
Alan Elbanhawy - Hollister CA, US
Thomas E. Grebs - , US
Nathan L. Kraft - , US
Dean E. Probst - West Jordan UT, US
Rodney S. Ridley - , US
Steven P. Sapp - Felton CA, US
Qi Wang - , US
Chongman Yun - , US
Peter H. Wilson - Wrightwood CA, US
Joseph A. Yedinak - , US
Babak S. Sani - Oakland CA, US
Richard Stokes - , US
Gary M. Dolny - , US
John Mytych - , US
Becky Losee - Cedar Hills UT, US
Adam Selsley - , US
Robert Herrick - Lehi UT, US
James J. Murphy - South Jordan UT, US
Gordon K. Madson - Riverton UT, US
Bruce D. Marchant - Murray UT, US
Christopher L. Rexer - , US
Christopher B. Kocon - Murray PA, US
Debra S. Woolsey - Draper UT, US

International Classification:

H01L 21/336
H01L 21/311

US Classification:

438270, 438694, 438703, 257E21249, 257E21419

Abstract:

A method for forming thick oxide at the bottom of a trench formed in a semiconductor substrate includes forming a conformal oxide film by a sub-atmospheric chemical vapor deposition process that fills the trench and covers a top surface of the substrate. The method also includes etching the oxide film off the top surface of the substrate and inside the trench to leave a substantially flat layer of oxide having a target thickness at the bottom of the trench.