Carter W Kaanta

US Patent:

6429473, Aug 6, 2002

Filed:

Jul 30, 1996

Appl. No.:

08/690629

Inventors:

John Edward Cronin - Milton VT
Carter Welling Kaanta - Colchester VT
Brian John Machesney - Burlington VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 27108

US Classification:

257296, 257309

Abstract:

A semiconductor chip with uniform topology includes a memory cell having a stacked capacitor self-aligned with a bitline. Thick insulation on the bitline and on interconnect wiring on supports circuits of the chip serves to provide the uniform topology and to provide for the self-alignment of the capacitor and bitline. Bitlines and support circuit interconnect wiring are both formed from the same level of metal but they are patterned in separate masking steps. The stacked capacitors are separated from each other by less than the minimum dimension of the photolithographic system used for fabrication.

US Patent:

6576848, Jun 10, 2003

Filed:

Nov 22, 1996

Appl. No.:

08/755052

Inventors:

John Edward Cronin - Milton VT
John Andrew Hiltebeitel - South Burlington VT
Carter Welling Kaanta - Colchester VT
James Gardner Ryan - Newtown CT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01R 909

US Classification:

174261, 174262, 174264, 361767, 361771

Abstract:

A wiring structure with crossover capability is disclosed. The wiring utilizes a connection stud in a contact layer, beneath the plane of the otherwise-intersecting lines as a crossover. Thus, a first wire in a first metallization layer passes below a second wire in a second metallization layer by overlapping contact with the connection stud in the contact layer. In manufacturing the wiring structure of the present invention, no intervening insulative or via layers are used between the contact layer, the first metallization layer and the second metallization layer. However, care must be taken in device layout on the substrate to ensure that the connection stud is located above isolation areas rather than active device areas.

US Patent:

54666368, Nov 14, 1995

Filed:

Sep 17, 1992

Appl. No.:

7/946993

Inventors:

John E. Cronin - Milton VT
Carter W. Kaanta - Colchester VT
Donald M. Kenney - Shelburne VT
Michael L. Kerbaugh - Jericho VT
Howard S. Landis - Underhill VT
Brian J. Machesney - Burlington VT
Paul Parries - Wappingers Falls NY
Rosemary A. Previti-Kelly - Richmond VT
John F. Rembetski - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2144

US Classification:

437187

Abstract:

A semiconductor fabrication process for forming borderless contacts (130, 170, 172) using a removable mandrel (110). The process involves depositing a mandrel on an underlying barrier layer (100) designed to protect underlying structures (40) formed on a substrate (24). The mandrel is made from a material that will etch at a faster rate than the barrier layer so as to permit the formation of openings in the mandrel to be stopped on the barrier layer without penetrating such layer. After depositing a contact (130) in a first opening (120) formed in the mandrel, a second opening (140) is formed and a second contact (170) is deposited therein. Thereafter, the mandrel is removed and replaced with a layer of solid dielectric material (180).

US Patent:

47583061, Jul 19, 1988

Filed:

Aug 17, 1987

Appl. No.:

7/086120

Inventors:

John E. Cronin - Milton VT
Carter W. Kaanta - Colchester VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

B44C 122
C03C 1500
C03C 2506
C23F 102

US Classification:

156643

Abstract:

A method of forming a conductive structure on a substrate by using both of the via-filling and stud-forming metallization techniques. A stud that is approximately one-half the thickness of the final stud is defined on a conductive layer. The stud-forming mask is left in place. Then the sidewalls of the mask are positively tapered, and an insulator layer is deposited on the substrate. The insulator is then etched to expose the stud forming mask, and the mask is removed. The sidewalls of the vias thus defined in the insulator layer are then positively tapered. By positively tapering both the stud mask prior to insulator deposition and the insulator via prior to metal deposition, insulator gap-fill and metal hole-fill problems are eliminated.

US Patent:

57958300, Aug 18, 1998

Filed:

Jul 26, 1996

Appl. No.:

8/686481

Inventors:

John E. Cronin - Milton VT
Carter W. Kaanta - Colchester VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 213065
C03C 2506

US Classification:

438696

Abstract:

A method of forming sub-lithographic elements and spaces therebetween where the pitch may be reduced with continuously adjustable line and space dimensions, and a structure resulting from the method, are disclosed. A plurality of spaced convertible members are formed on a substrate. A portion of each member is then converted, thereby reducing the dimensions of the unconverted portion of the member while increasing the width of the member plus its converted layer. A conformal layer of material is then deposited over the converted members, followed by directional etching of the conformal layer. The unconverted portion of the member is then removed. The line and space dimensions can be continuously adjusted by altering either or both of the member's converted layer and conformal layer.

US Patent:

57604754, Jun 2, 1998

Filed:

Nov 14, 1994

Appl. No.:

8/339317

Inventors:

John Edward Cronin - Milton VT
Carter Welling Kaanta - Colchester VT
Michael Albert Leach - Bristol VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2348

US Classification:

257758

Abstract:

The present invention provides a conductive structure for use in semiconductor devices. The structure can be used to interconnect the various diffusion regions or electrodes of devices formed on a processed semiconductor substrate to a layer of metal, to interconnect overlying layers of metal or to provide the gate electrode of an FET device formed on the surface of a semiconductor substrate. Various embodiments of the invention are described, but in broad form the active metallurgy of the present invention comprises a thin continuous layer to titanium--titanium nitride and a thick layer of a refractory metal, e. g. tungsten, overlying the titanium nitride layer.

US Patent:

57599114, Jun 2, 1998

Filed:

Aug 22, 1995

Appl. No.:

8/517782

Inventors:

John Edward Cronin - Milton VT
Carter Welling Kaanta - Colchester VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2128
H01L 2131

US Classification:

438622

Abstract:

A method is provided for filling undesired sublithographic contact hole defects in a semiconductor structure caused by misalignment and undesirable overlap of metal line images over contact openings during photolithographic patterning. Unwanted contact between conductive metallization levels through these defects is thereby diminished. The method also provides self-alignment of the lines and contact holes for subsequent formation of stud via connections through which contact is desired to underlying metallization levels. Deposition of a conformal sacrificial material film fills the small, undesired sublithographic contact hole image formed and covers both mask surfaces through which the misaligned line image and contact opening were etched. Isotropic etching removes the conformal layer from all planar surfaces except those of the undesired sublithographic contact hole image. Translation into the underlying insulating layer results in the formation of only contact holes through which contact with underlying substrate metallization is desired.

US Patent:

53344677, Aug 2, 1994

Filed:

Feb 25, 1993

Appl. No.:

8/022516

Inventors:

John E. Cronin - Milton VT
Paul A. Farrar - So. Burlington VT
Carter W. Kaanta - Colchester VT
James G. Ryan - Essex Junction VT
Andrew J. Watts - Milton VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G03F 900

US Classification:

430 5

Abstract:

A gray level mask suitable for photolithography is constructed of a transparent glass substrate which supports plural levels of materials having different optical transmissivities. In the case of a mask employing only two of these levels, one level may be constructed of a glass made partially transmissive by substitution of silver ions in place of metal ions of alkali metal silicates employed in the construction of the glass. The second layer may be made opaque by construction of the layer of a metal such as chromium. The mask is fabricated with the aid of a photoresist structure which is etched in specific regions by photolithographic masking to enable selective etching of exposed regions of the level of materials of differing optical transmissivities. Various etches are employed for selective etching of the photoresist, the metal of one of the layers, and the glass of the other of the layers. The etches include plasma etch with chloride ions to attack the chromium of the opaque layer, compounds of fluorine to attack the glass layer, and reactive ion etching with oxygen to attack the photoresist structure.