Cesar A Garza

US Patent:

6593033, Jul 15, 2003

Filed:

Sep 21, 1999

Appl. No.:

09/399840

Inventors:

Zhiliu Ma - Plano TX
Anthony Yen - Austin TX
Cesar Garza - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G03F 900

US Classification:

430 5

Abstract:

An embodiment of the instant invention is a mask having a pattern which is transferred to a layer overlying a semiconductor wafer, the mask comprising: a transmissive portion (structure of FIG. 1), the transmissive portion allowing energy which impinges upon the transmission portion to substantially pass through the transmissive portion; a substantially non-transmissive portion (structure of FIG. 1); a semi-transmissive portion (structure of FIG. 1) situated between the transmissive portion and the substantially non-transmissive portion, energy passing through the semi-transmissive portion having a phase; and wherein the phase of energy which passes through the semi-transmissive portion is out of phase with the phase of energy which passes through the transmissive portion. Preferably, the phase of the energy which passes through the semi-transmissive portion is around 180 degrees out of phase with energy which passes through the transmissive portion.

US Patent:

48913030, Jan 2, 1990

Filed:

May 26, 1988

Appl. No.:

7/199087

Inventors:

Cesar M. Garza - Plano TX
Monte A. Douglas - Coppell TX
Roland Johnson - Sachse TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G03C 516

US Classification:

430312

Abstract:

A method for patterning an integrated circuit workpiece (10) includes forming a first layer (16) of organic material on the workpiece surface to a depth sufficient to allow a substantially planar outer surface (36) thereof. A second, polysilane-based resist layer (22) is spin-deposited on the first layer (16). A third resolution layer (24) is deposited on the second layer (22). The resolution layer (24) is selectively exposed and developed using standard techniques. The pattern in the resolution layer (24) is transferred to the polysilane layer (22) by either using exposure to deep ultraviolet or by a fluorine-base RIE etch. This is followed by an oxygen-based RIE etch to transfer the pattern to the surface (18) of the workpiece (10).

US Patent:

47707399, Sep 13, 1988

Filed:

Feb 3, 1987

Appl. No.:

7/010378

Inventors:

Kevin J. Orvek - Plano TX
Cesar M. Garza - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

B44C 122
C03C 1500
C03C 2506
C23F 102

US Classification:

156643

Abstract:

The present invention relates to a bilayer photoresist process, wherein a first planarizing resist layer is applied to a base and a second or top photoresist layer is applied over the first. The top layer resist is sensitive to deep UV light, while the planarizing layer resist is sensitive to near UV or violet light. The top layer, by use of a dye or other means, is opaque to predetermined near UV or violet wavelengths by which the planarizing layer is illuminated. The top layer is patterned using deep UV light. A flood exposure of the predetermined near UV or violet wavelengths is then used to transfer the pattern of the top layer to the bottom planarizing resist layer. Improved resolution is achieved by the use of deep UV light for patterning the top layer. Less costly yet faster illumination of the planarizing layer is accomplished by using near UV or violet light. Additionally pattern degradation due to spurious reflections normally occurring from near UV exposure of the top layer is avoided.

US Patent:

50949365, Mar 10, 1992

Filed:

Jun 26, 1990

Appl. No.:

7/544085

Inventors:

George R. Misium - Richardson TX
Cesar M. Garza - Plano TX
Cecil J. Davis - Greenville TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G03F 736

US Classification:

430325

Abstract:

A process for silylation of positive or negative photosensitive resist layer on a semiconductor wafer after the resist layer has been exposed to radiant energy through a mask which includes introducing a silylating agent to the wafer at high pressure over 760 torr and, usually, at temperatures less than 180. degree. C. Increased pressure increases the rate of silylation, allows practical use of lower process temperatures, and, therefore, allows better process control. Also an apparatus is disclosed for applying the high pressure silylation process to a wafer.

US Patent:

50857290, Feb 4, 1992

Filed:

Sep 7, 1990

Appl. No.:

7/579120

Inventors:

Cesar M. Garza - Plano TX
Ricky A. Jackson - Garland TX
Ryan E. Priebe - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21306
B44C 122
B05D 306
G03C 500

US Classification:

156628

Abstract:

A system and method whereby the uniformity of the silylating agent throughout the reaction chamber and primarily at the surface of the wafer is significantly improved to provide a significant improvement in the line width uniformity. In accordance with a first embodiment of the invention, this is accomplished by stagnant silylation wherein the silylating agent is introduced into the reaction chamber and the reaction chamber is then sealed during the entire time required to carry out the silylation. The advantage of this approach is optimum uniformity since once equilibrium has been reached, there is no net change of flow or pressure of the silylating agent across the wafer. Another advantage is reduction in the total consumption of the silylating and carrier gases. In accordance with a second embodiment of the invention, the silylating agent flows laminarly across the surface of the wafer to provide uniformity of the silylating agent at the wafer surface. This is accomplished by introducing the silylating agent and carrier gas along one side of the wafer and uniformly flowing the gases across the entire wafer due to a pressure differential across the wafer from the location(s) of gas entry into the reaction chamber to the location(s) of gas exit from the reaction chamber, for example.

US Patent:

48820083, Nov 21, 1989

Filed:

Jul 8, 1988

Appl. No.:

7/216884

Inventors:

Cesar M. Garza - Plano TX
Monte A. Douglas - Coppell TX
Lee M. Loewenstein - Plano TX
Cecil J. Davis - Greenville TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

B44C 122
H01L 21306
C03C 1500
B29C 3700

US Classification:

156643

Abstract:

A process for developing a photolithographic pattern on the surface of an exposed workpiece in a process chamber; disposing the workpiece in a process chamber; heating the workpiece and introducing a silylating agent to the process chamber and to a face of the workpiece to be processed; generating activated species from a source of oxygen; and introducing the activated species to the face of the workpiece.

US Patent:

57167389, Feb 10, 1998

Filed:

Jun 7, 1996

Appl. No.:

8/660294

Inventors:

Cesar M. Garza - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G03F 900

US Classification:

430 5

Abstract:

A mask for use in semiconductor fabrication which includes a light transparent substrate, preferably glass, having a border and light semitransparent material having light transmissivity preferably in the range of from about 6 to about 10 percent disposed thereon within the border. A light opaque layer which is sensitive to light and which can be patterned and have a predetermined portion thereof removed in response to selective exposure to light is disposed along substantially the entire border of the substrate. The mask can further include a region of light semitransparent material disposed around the border and under the light opaque layer. The light opaque layer is preferably a photosensitive polyimide.

Address:

2828 Hood St APT 607, Dallas, TX 75219

VIN:

1GNFC13057R384048

Make:

CHEVROLET

Model:

TAHOE

Year:

2007