Chakra R Srivatsa

US Patent:

6523055, Feb 18, 2003

Filed:

Jan 20, 1999

Appl. No.:

09/235417

Inventors:

Robert K. Yu - Newark CA
Satish Padmanabhan - Sunnyvale CA
Chakra R. Srivatsa - San Jose CA
Shailesh I. Shah - Sunnyvale CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 738

US Classification:

708603, 708620, 708625

Abstract:

A multiplication accumulation circuit (abbreviated as âMACâ) has five input buses that carry signals for operands A, B, C, D and E, a control bus that carries signals for controlling the operations performed on the received operands, and an output bus that carries a signal generated by the MAC. Each of operands A, B, C and D can be four different operands that are used as follows by the MAC: (1) to perform two multiplications simultaneously, and (2) to perform an addition of the products of the two multiplications and the fifth operand E, e. g. generate on the output bus a signal of value A*C+B*D+E. Alternatively, operands A and B can be, respectively, the upper and lower halves of a first double word to be used as a multiplicand. Similarly, operands C and D can be the upper and lower halves of a second double word to be used as a multiplier. In this case, the four operands A, B, C and D are used as follows by the MAC: (1) to perform a single multiplication of the first double word with the second double word, and (2) to perform an addition of the product of the double word multiplication, and the fifth operand E, e. g.

US Patent:

58385800, Nov 17, 1998

Filed:

Jun 20, 1996

Appl. No.:

8/667908

Inventors:

Chakra R. Srivatsa - San Jose CA

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

G06F 1750

US Classification:

364489

Abstract:

A method includes operating a general purpose computer system to minimize signal-propagation delay time of a long line of a simulated circuit. A design engineer empirically derives two rule bases, the first of which determines whether to divide the long line into two or more segments by inserting repeater amplifiers into a long line to minimize the propagation delay through the line. The second rule base relates optimum amplifier size for driving long lines to line length. These rule bases are stored in a main memory of the computer system. The computer system is configured to apply the first rule base to the long line to determine whether to divide the long line into two or more segments by inserting repeater amplifiers, and to apply the second rule base to optimize the size of each of the repeater amplifiers. The resulting long line, segmented by size-optimized repeater amplifiers, provides minimal signal-propagation delay.

US Patent:

H17965, Jul 6, 1999

Filed:

May 2, 1996

Appl. No.:

8/646643

Inventors:

Chakra R. Srivatsa - San Jose CA
Ronald J. Melanson - Woodside CA
David J. Greenhill - Portola Valley CA

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

H03K 3037

US Classification:

327215

Abstract:

Circuits and methods for eliminating hold time violations are disclosed. A DE-type flip-flop latches a data input signal on a data input terminal a fraction of a clock period before a triggering edge of the clock signal. The DE-type flip-flop provides a data output signal for a full clock period beginning after the triggering edge of the clock signal. The DE-type flip-flop includes a latch having its data output terminal coupled to the data input terminal of a flip-flop. The flip-flop clock input pin and the latch enable terminal of the latch are connected to a clock line. The DE-type flip-flop used in place of a standard flip-flop, in which a hold time violation occurs, eliminates the hold time violation.

US Patent:

6009253, Dec 28, 1999

Filed:

Jun 20, 1996

Appl. No.:

8/669897

Inventors:

Chakra R. Srivatsa - San Jose CA
James A. Bauman - Palo Alto CA

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

G06F 1750

US Classification:

39550007

Abstract:

An IC includes a plurality of functional blocks each having a discrete block-level architecture. The functional blocks are connected to one another via metal interconnect lines defined by an interconnect architecture. One or more of the functional blocks includes a spare (i. e. , unused) repeater amplifier. Where a repeater amplifier inserted in a particular long line of the interconnect structure would decrease the signal propagation delay through the long line, the interconnect architecture is modified so that the long line is routed through the spare repeater amplifier. Such modification decreases the signal propagation delay of the long line without requiring a modification of the block-level architecture.