Chang Ho Jung

US Patent:

6335899, Jan 1, 2002

Filed:

Apr 19, 2000

Appl. No.:

09/552266

Inventors:

Chang Ho Jung - Fort Collins CO

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G11C 700

US Classification:

36523005, 365205, 365206, 365214, 365217

Abstract:

A compensation capacitance is utilized in a multiport memory device to compensate for the effect of bit line coupling capacitance. A first compensation capacitance is applied between a read bit line and a write bar bit line, and a second compensation capacitance is applied between a write bit line and a read bar bit line to compensate for the effect of bit line capacitance that adversely affects the differential voltage swing at a the read bit line. In one embodiment, the compensation capacitances are equal to the value of the compensation capacitances. In an alternative embodiment, each compensation capacitance comprises two compensation capacitors additively combined in parallel each having a value of one-half of the coupling capacitance. The compensation capacitance may be variable so that compensation of the coupling capacitance may be optimized after fabrication of the integrated circuit.

US Patent:

6518795, Feb 11, 2003

Filed:

Jun 15, 2001

Appl. No.:

09/882977

Inventors:

Chang Ho Jung - Fort Collins CO

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H03K 1900

US Classification:

326 93, 326113, 327202, 327298

Abstract:

The present invention discloses a novel method and system for accessing a semiconductor device at multiple operating speeds. The novel method and system of the present invention allows access to a semiconductor device by a pipeline circuit in which modification of the pipeline circuitry is not required to achieve multiple operating speeds. An example of the invention may be the utilization of an internal clock to control internal pipeline which may allow adjustment of an effective operating speed of a semiconductor device.

US Patent:

6586970, Jul 1, 2003

Filed:

Sep 17, 2001

Appl. No.:

09/953842

Inventors:

Chang Ho Jung - Fort Collins CO

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H03K 19094

US Classification:

326105, 326106, 326108

Abstract:

The present invention describes a multi-stage decoder and method of decoding utilizing a pseudo NAND or pseudo AND gate in one of the stages. This invention presents a decoder comprising a first stage circuit having two or more first inputs which generates one or more first outputs; and a second stage circuit having at least one second input and at least one second output, wherein the one or more first outputs are the same as the at least one second input, wherein at least one of the group consisting of the first stage circuit and the second stage circuit includes either a pseudo AND gate or a pseudo NAND gate. This invention presents a method of decoding, comprising the steps of generating a signal responsive to two or more address bits and enabling a decoder by the generated signal.

US Patent:

6809983, Oct 26, 2004

Filed:

Mar 25, 2003

Appl. No.:

10/397483

Inventors:

Chang Ho Jung - Fort Collins CO

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G11C 800

US Classification:

36523005, 36518904

Abstract:

A clock generating circuit for a pseudo dual port memory incorporates feedback, delays, and latches to ensure that the write (read) operation clock pulse is sufficiently spaced in time from the read (write) operation clock. The clock generating circuit receives an external clock, a read enable signal, a write enable signal, and a reset signal as inputs. Advantages include minimization of the clock cycle time and operation unaffected by the duty ratio of an external clock. Delay circuitry may be added such that the generated clock signal has sufficient fan out and is sufficiently stable.

US Patent:

6963515, Nov 8, 2005

Filed:

May 8, 2003

Appl. No.:

10/431945

Inventors:

Jeffrey Scott Brown - Fort Collins CO, US
Craig R. Chafin - Fort Collins CO, US
Chang Ho Jung - Fort Collins CO, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G11C008/00

US Classification:

36523003, 36523005, 36523006

Abstract:

The present invention is a method and system for providing a scalable memory building block device. The memory building block device includes a plurality of separate memory arrays, decode logic for selecting only one bit from the plurality of memory arrays, and output means for providing only one bit as an output of the memory building block device, such that the memory building block device generates as its output only one bit.

US Patent:

7061822, Jun 13, 2006

Filed:

Aug 4, 2004

Appl. No.:

10/911457

Inventors:

Chang Ho Jung - Fort Collins CO, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G11C 8/00

US Classification:

36523005, 36518904, 365194

Abstract:

A clock generating circuit for a pseudo dual port memory incorporates feedback, delays, and latches to ensure that the write (read) operation clock pulse is sufficiently spaced in time from the read (write) operation clock. The clock generating circuit receives an external clock, a read enable signal, a write enable signal, and a reset signal as inputs. Advantages include minimization of the clock cycle time and operation unaffected by the duty ratio of an external clock. Delay circuitry may be added such that the generated clock signal has sufficient fan out and is sufficiently stable.

US Patent:

7251193, Jul 31, 2007

Filed:

Nov 17, 2005

Appl. No.:

11/282333

Inventors:

Chang Ho Jung - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

G11C 8/00

US Classification:

3652335, 365233, 365194

Abstract:

A pseudo-dual port memory performs both a first memory access operation and a second memory access operation in a single period of an externally supplied clock signal CLK. The signal CLK is used to latch a first address for the first operation and a second address for the second operation. Control circuitry generates first control signals that initiate the first operation. The time duration of the first operation depends upon a delay through a delay circuit. A precharge period follows termination of the first operation. The time duration of the precharge period depends upon a propagation delay through the control circuit. The memory access of the second operation is initiated following termination of the precharging. The time duration of the second memory access depends on a delay through the delay circuit. The time when the second operation is initiated is independent of the duty cycle of CLK.

US Patent:

7319632, Jan 15, 2008

Filed:

Nov 17, 2005

Appl. No.:

11/282345

Inventors:

Chang Ho Jung - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

G11C 8/00

US Classification:

36523005, 365154

Abstract:

A pseudo-dual port memory has a first port, a second port, and an array of six-transistor memory cells. A first memory access is initiated upon a rising edge of a first clock signal received onto the first port. A second memory access is initiated in response to a rising edge of a second clock signal received onto the second port. If the rising edge of the second clock signal occurs within a first period of time, then the second memory access is initiated immediately following completion of the first memory access in pseudo-dual port fashion. If the rising edge of the second clock signal occurs later within a second period of time, then the second memory access is delayed until after a second rising edge of the first clock signal. The durations of the first and second memory accesses do not depend on the duty cycles of the clock signals.