Dilip A. Amin - San Jose CA Chang Hong Wu - Cupertino CA Ross Heitkamp - Mountain View CA Michael Armstrong - Sunnyvale CA
Assignee:
Juniper Networks, Inc. - Sunnyvale CA
International Classification:
H03L 700
US Classification:
327143
Abstract:
A voltage sequencing circuit powers-up electrical systems by sequentially enabling a series of power supply lines to the electrical system. After each power supply line is enabled, the voltage sequencing circuit waits a pre-programmed delay time before enabling the next power supply line. The delay time allows the newly enabled power supply line to settle. Additionally, the voltage sequencing circuit constantly monitors previously enabled power supply lines while continuing to enable the remaining power supply lines. If any of the previously enabled lines fail, the voltage sequencing circuit disables the power supply line before reinitiating a complete power-up sequence.
Voltage Sequencing Circuit For Powering-Up Sensitive Electrical Components
Dilip A. Amin - San Jose CA Chang Hong Wu - Cupertino CA Ross Heitkamp - Mountain View CA Michael Armstrong - Sunnyvale CA
Assignee:
Juniper Networks, Inc. - Sunnyvale CA
International Classification:
H03L 700
US Classification:
327143
Abstract:
A voltage sequencing circuit powers-up electrical systems by sequentially enabling a series of power supply lines to the electrical system. After each power supply line is enabled, the voltage sequencing circuit waits a pre-programmed delay time before enabling the next power supply line. The delay time allows the newly enabled power supply line to settle. Additionally, the voltage sequencing circuit constantly monitors previously enabled power supply lines while continuing to enable the remaining power supply lines. If any of the previously enabled lines fail, the voltage sequencing circuit disables the power supply line before reinitiating a complete power-up sequence.
Fudan University
Professor
Cadence Design Systems
Architect
Xilinx Aug 2010 - Sep 2013
Senior Staff Engineer
Magma Design Automation 2003 - Aug 2010
Senior Consulting Staff
Aplus Design Technologies Feb 1998 - May 2003
Senior Engineer
Education:
University of California, Los Angeles 1995 - 1999
Doctorates, Doctor of Philosophy, Computer Science
Shanghai Jiao Tong University 1982 - 1989
Master of Science, Masters, Computer Science
University of California
Skills:
Eda Asic Verilog Tcl Fpga Logic Synthesis Soc Physical Design Vhdl C++ Debugging Semiconductors Vlsi Static Timing Analysis Rtl Design Field Programmable Gate Arrays Compilers Very Large Scale Integration Algorithms C Integrated Circuits