Charles M Callahan

US Patent:

20020129339, Sep 12, 2002

Filed:

Apr 3, 2001

Appl. No.:

09/825434

Inventors:

Charles Callahan - Seattle WA, US
Keith Shields - Seattle WA, US
Preston Briggs - Seattle WA, US

International Classification:

G06F009/44

US Classification:

717/127000

Abstract:

A system for conducting performance analysis for executing tasks. The analysis involves generating a variety of trace information related to performance measures, including parallelism-related information, during execution of the task. In order to generate the trace information, target source code of interest is compiled in such a manner that executing the resulting executable code will generate execution trace information composed of a series of events. Each event stores trace information related to a variety of performance measures for the one or more processors and protection domains used. After the execution trace information has been generated, the system can use that trace information and a trace information description file to produce useful performance measure information. The trace information description file contains information that describes the types of execution events as well as the structure of the stored information. The system uses the trace information description file to organize the information in the trace information file, extracts a variety of types of performance measure information from the organized trace information, and formats the extracted information for display. The system can use default or user-defined functions to extract and format trace information for display. After the system displays one or more types of performance measure information, a user of the system can then interact with the system in a variety of ways to obtain other useful performance analysis information.

US Patent:

20040064816, Apr 1, 2004

Filed:

Oct 1, 2003

Appl. No.:

10/676680

Inventors:

Gail Alverson - Seattle WA, US
Charles Callahan - Seattle WA, US
Susan Coatney - Federal Way WA, US
Brian Koblenz - Seattle WA, US
Richard Korry - Seattle WA, US
Burton Smith - Seattle WA, US

International Classification:

G06F009/00

US Classification:

718/102000

Abstract:

A method and system that prepares a task for being swapped out from processor utilization that is executing on a computer with multiple processors that each support multiple streams. The task has one or more teams of threads, where each team represents threads executing on a single processor. The task designates, for each stream that is executing a thread, one stream as a team master stream and one stream as a task master stream. For each team master stream, the task notifies the operating system that the team is ready to be swapped out when each other thread of the team has saved its state and has quit its stream. Finally, for the task master stream, the task notifies the operating system that the task is ready to be swapped when it has saved its state and each other team has notified that it is ready to be swapped out.

US Patent:

20040064818, Apr 1, 2004

Filed:

Sep 16, 2003

Appl. No.:

10/663895

Inventors:

Gail Alverson - Seattle WA, US
Charles Callahan - Seattle WA, US
Susan Coatney - Federal Way WA, US
Brian Koblenz - Seattle WA, US
Richard Korry - Seattle WA, US
Burton Smith - Seattle WA, US

International Classification:

G06F009/00

US Classification:

718/107000

Abstract:

A method and system that prepares a task for being swapped out from processor utilization that is executing on a computer with multiple processors that each support multiple streams. The task has one or more teams of threads, where each team represents threads executing on a single processor. The task designates, for each stream that is executing a thread, one stream as a team master stream and one stream as a task master stream. For each team master stream, the task notifies the operating system that the team is ready to be swapped out when each other thread of the team has saved its state and has quit its stream. Finally, for the task master stream, the task notifies the operating system that the task is ready to be swapped when it has saved its state and each other team has notified that it is ready to be swapped out.

US Patent:

20040078795, Apr 22, 2004

Filed:

Oct 10, 2003

Appl. No.:

10/683774

Inventors:

Gail Alverson - Seattle WA, US
Charles Callahan - Seattle WA, US
Susan Coatney - Federal Way WA, US
Brian Koblenz - Seattle WA, US
Richard Korry - Seattle WA, US
Burton Smith - Seattle WA, US

International Classification:

G06F009/00

US Classification:

718/100000

Abstract:

A method and system that prepares a task for being swapped out from processor utilization that is executing on a computer with multiple processors that each support multiple streams. The task has one or more teams of threads, where each team represents threads executing on a single processor. The task designates, for each stream that is executing a thread, one stream as a team master stream and one stream as a task master stream. For each team master stream, the task notifies the operating system that the team is ready to be swapped out when each other thread of the team has saved its state and has quit its stream. Finally, for the task master stream, the task notifies the operating system that the task is ready to be swapped when it has saved its state and each other team has notified that it is ready to be swapped out.

US Patent:

20040088711, May 6, 2004

Filed:

Sep 10, 2003

Appl. No.:

10/659407

Inventors:

Gail Alverson - Seattle WA, US
Charles Callahan - Seattle WA, US
Susan Coatney - Federal Way WA, US
Brian Koblenz - Seattle WA, US
Richard Korry - Seattle WA, US
Burton Smith - Seattle WA, US

International Classification:

G06F015/16

US Classification:

718/107000, 709/231000

Abstract:

A method and system that prepares a task for being swapped out from processor utilization that is executing on a computer with multiple processors that each support multiple streams. The task has one or more teams of threads, where each team represents threads executing on a single processor. The task designates, for each stream that is executing a thread, one stream as a team master stream and one stream as a task master stream. For each team master stream, the task notifies the operating system that the team is ready to be swapped out when each other thread of the team has saved its state and has quit its stream. Finally, for the task master stream, the task notifies the operating system that the task is ready to be swapped when it has saved its state and each other team has notified that it is ready to be swapped out.

US Patent:

20040093603, May 13, 2004

Filed:

Sep 16, 2003

Appl. No.:

10/663897

Inventors:

Gail Alverson - Seattle WA, US
Charles Callahan - Seattle WA, US
Susan Coatney - Federal Way WA, US
Brian Koblenz - Seattle WA, US
Richard Korry - Seattle WA, US
Burton Smith - Seattle WA, US

International Classification:

G06F009/46

US Classification:

718/107000

Abstract:

A method and system that prepares a task for being swapped out from processor utilization that is executing on a computer with multiple processors that each support multiple streams. The task has one or more teams of threads, where each team represents threads executing on a single processor. The task designates, for each stream that is executing a thread, one stream as a team master stream and one stream as a task master stream. For each team master stream, the task notifies the operating system that the team is ready to be swapped out when each other thread of the team has saved its state and has quit its stream. Finally, for the task master stream, the task notifies the operating system that the task is ready to be swapped when it has saved its state and each other team has notified that it is ready to be swapped out.

US Patent:

20040093605, May 13, 2004

Filed:

Oct 29, 2003

Appl. No.:

10/697890

Inventors:

Gail Alverson - Seattle WA, US
Charles Callahan - Seattle WA, US
Simon Kahan - Seattle WA, US
Brian Koblenz - Seattle WA, US
Allan Porterfield - Bellevue WA, US
Burton Smith - Seattle WA, US

International Classification:

G06F009/44

US Classification:

719/310000

Abstract:

Various techniques for manipulating data using access states of memory, access control fields of pointers and operations, and exception raising and exception trapping in a multithreaded computer system. In particular, the techniques include synchronization support for a thread blocked in a word, demand evalution of values, parallel access of multiple threads to a list synchronized and unsynchronized access to a data buffer, use of fowarding to avoid checking for an end of a buffer, use of sentinel work to detect access past a data structure, concurrent access to a word of memory using different synchronization access modes, and use of trapping to detect access to restricted memory.

US Patent:

20040098721, May 20, 2004

Filed:

Oct 30, 2003

Appl. No.:

10/697902

Inventors:

Gail Alverson - Seattle WA, US
Charles Callahan - Seattle WA, US
Simon Kahan - Seattle WA, US
Brian Koblenz - Seattle WA, US
Allan Porterfield - Bellevue WA, US
Burton Smith - Seattle WA, US

International Classification:

G06F009/00
G06F013/24

US Classification:

718/102000, 710/260000

Abstract:

Various techniques for manipulating data using access states of memory, access control fields of pointers and operations, and exception raising and exception trapping in a multithreaded computer system. In particular, the techniques include synchronization support for a thread blocked in a word, demand evaluation of values, parallel access of multiple threads to a list, synchronized and unsynchronized access to a data buffer, use of forwarding to avoid checking for an end of a buffer, use of sentinel word to detect access past a data structure, concurrent access to a word of memory using different synchronization access modes, and use of trapping to detect access to restricted memory.