Charles R Erickson

US Patent:

57899380, Aug 4, 1998

Filed:

Sep 4, 1996

Appl. No.:

8/707545

Inventors:

Charles R. Erickson - Fremont CA
Robert O. Conn - Los Gatos CA
Lois D. Cartier - Los Gatos CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 738

US Classification:

326 40

Abstract:

A self-addressing memory device is provided that can provide blocks of data starting from more than one initial location in the device, and may have the option of reading in either direction. This memory device can efficiently store multiple bitstreams, which may be of different sizes, that are used to configure one or more configurable logic devices. Each stored bitstream can be accessed in any order. In one embodiment, the configurable logic device is a Field Programmable Gate Array ("FPGA"). In one embodiment, the memory device is a Read-Only Memory ("ROM") that is either read up from all zeros or down from all ones. In one embodiment, the ROM includes a bidirectional chip enable chain that permits cascading multiple ROMs.

US Patent:

53312201, Jul 19, 1994

Filed:

Feb 12, 1993

Appl. No.:

8/016643

Inventors:

Kerry M. Pierce - Fremont CA
Charles R. Erickson - Fremont CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 19092
H03K 1900

US Classification:

307475

Abstract:

Power or ground voltage can fluctuate when many high capacitance terminals of an integrated circuit device move simultaneously from one logic state to another. This occurs particularly after release of a global high impedance state of output buffers where output signals have been passively driven to a selected logic state. To prevent supply and ground voltage variations, the buffers are provided with means for operating in a slow response (high slew) mode. A slew rate control circuit moves the buffer to slow response mode in response to the high impedance signal. When the slew rate control circuit receives a signal ending the high impedance state of the buffer, it applies a delay to this signal, and after the delay time allows the buffer to move to a fast response mode. The slow buffer response and resulting slow voltage change when high capacitance terminals move to a new logic state prevents fluctuation of power or ground voltage in response to simultaneous switching of many terminals.

US Patent:

56002718, Feb 4, 1997

Filed:

Sep 15, 1995

Appl. No.:

8/528580

Inventors:

Charles R. Erickson - Fremont CA
Peter H. Alfke - Los Altos Hills CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 19084

US Classification:

327108

Abstract:

An input interface circuit for a logic device having a configuration of pull-up and pull-down devices for defining the logic level based on an undriven input signal where the pull-up and pull-down devices are independently and separately programmable to follow the input signal (e. g. , a keeper circuit), or follow the inverse of the input signal, or programmed permanently on, or programmed permanently off. The interface circuit can be used to provide a known and programmable output signal for an IC input (or internal line) that does not have a known driving source. By allowing this degree of flexibility, the input interface circuit of the present invention, under programmed control, generates an output signal with positive or negative feedback based on the input signal; or the input interface circuit provides a constant high or constant low signal output, or can oscillate or provide a high impedance response as output. In cases when the input pin (or internal line) is not being driven by a bus or source driver, the input interface provides a number of flexible configurations for supplying predetermined outputs. Within a programmable logic device, a separate input interface circuit is provided with each external pad (or internal line) that provides signals within the integrated circuit originating from associated input pins.

US Patent:

55661238, Oct 15, 1996

Filed:

Feb 10, 1995

Appl. No.:

8/386972

Inventors:

Philip M. Freidin - Sunnyvale CA
Edmond Y. Cheung - San Jose CA
Charles R. Erickson - Fremont CA
Tsung-Lu Syu - Fremont CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G11C 800
G11C 700

US Classification:

36523005

Abstract:

A configurable logic block (CLB) in the dual port mode uses one address to write the same information in a first RAM and a second RAM. The input signals provided to the second function generator can be used to read, independently from and even asynchronously with, the write operation, thereby dramatically increasing the speed of applications using the two sets of RAM. A CLB in the synchronous mode latches the appropriate address and data signals, and generates a strobed write enable signal. The strobed signal is self-timed, i. e. the write operation is fully automatic, thereby ensuring that a write operation occurs within one clock cycle.

US Patent:

55239633, Jun 4, 1996

Filed:

Jun 7, 1995

Appl. No.:

8/479896

Inventors:

Hung-Cheng Hsieh - late of Sunnyvale CA
by William S. Carter - Santa Clara CA
Charles R. Erickson - Fremont CA
Edmond Y. Cheung - San Jose CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 750

US Classification:

364786

Abstract:

Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things for performing arithmetic functions which use logic for generating the carry function. When a large number of bits is to be processed, the carry function typically causes significant delay or requires significant additional components to achieve a result at high speed. The present invention provides dedicated hardware within the logic blocks for performing the carry function quickly and with a minimum number of components. The invention takes advantage of the fact that a carry signal to be added to two bits can be propagated to the next more significant bit when the two binary bits to be added are unequal, and that one of the bits can serve as the carry signal when the bits are equal.

US Patent:

59695439, Oct 19, 1999

Filed:

Feb 3, 1997

Appl. No.:

8/790873

Inventors:

Charles R. Erickson - Fremont CA
Peter H. Alfke - Los Altos Hills CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 190175

US Classification:

326 83

Abstract:

An input interface circuit for a logic device having a configuration of pull-up and pull-down devices for defining the logic level based on an undriven input signal where the pull-up and pull-down devices are independently and separately programmable to follow the input signal (e. g. , a keeper circuit), or follow the inverse of the input signal, or programmed permanently on, or programmed permanently off. The interface circuit can be used to provide a known and programmable output signal for an IC input (or internal line) that does not have a known driving source. By allowing this degree of flexibility, the input interface circuit of the present invention, under programmed control, generates an output signal with positive or negative feedback based on the input signal; or the input interface circuit provides a constant high or constant low signal output, or can oscillate or provide a high impedance response as output. In cases when the input pin (or internal line) is not being driven by a bus or source driver, the input interface provides a number of flexible configurations for supplying predetermined outputs. Within a programmable logic device, a separate input interface circuit is provided with each external pad (or internal line) that provides signals within the integrated circuit originating from associated input pins.

US Patent:

59202017, Jul 6, 1999

Filed:

Sep 23, 1997

Appl. No.:

8/935567

Inventors:

Alok Mehrotra - Los Gatos CA
Charles R. Erickson - Fremont CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G01R 2722

US Classification:

324765

Abstract:

In a field programmable gate array, a test circuit for testing the signal path of a line, through a pass gate, and onto a second line. A memory cell outputs at a V. sub. GG level, where V. sub. GG. gtoreq. V. sub. DD +V. sub. TN. In order to dynamically test the signal path, three transistors and two test signals are used to apply either 0 volts or V. sub. GG to control the pass gate. Two of the transistors are coupled to the memory cell and the pass gate, whereas the third transistor is coupled to the first and second transistors and ground. The two test signals and an inverter control these transistors so that the memory state can be changed to dynamically switch the pass gate according to the test configuration. An electrical signal is then sent through the signal path under test, and the result is monitored.

US Patent:

62126393, Apr 3, 2001

Filed:

Jun 29, 1999

Appl. No.:

9/342336

Inventors:

Charles R. Erickson - Fremont CA
Danesh Tavana - Mountain View CA
Victor A. Holen - Los Gatos CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H04K 100

US Classification:

713200

Abstract:

A method of communicating encrypted configuration data between a programmable logic device (PLD) and a storage device is included in one part of the invention. The method includes the following steps. Transmit encrypted configuration data stored in a storage device to the PLD. Decrypt the encrypted configuration data to generate a copy of the configuration data in the PLD. Configure the PLD using the copy of the configuration data. In one embodiment, the PLD transmits a key to the storage device. In another embodiment the key is separately entered into the storage device and the PLD and never transmitted between the PLD and the storage device. In another embodiment, the key is entered only into the PLD. The key is used to encrypt the configuration data.