Charles E May

US Patent:

6338992, Jan 15, 2002

Filed:

Nov 29, 2000

Appl. No.:

09/726107

Inventors:

Shafqat Ahmed - Beaverton OR
Hemanshu D. Bhatt - Troutdale OR
Charles E. May - Gresham OR
Robindranath Banerjee - Gresham OR

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 218238

US Classification:

438210, 438201, 438258, 438593

Abstract:

An improvement to a process for manufacturing complementary metal oxide semiconductor devices on a monolithic substrate, where the improved process forms nonvolatile memory devices and programmable logic devices. The improvement includes exposing gate electrodes of a selected portion of the complementary metal oxide semiconductor devices at a point in the process where the gate electrodes have been previously covered by a protective material layer. A capacitive material layer is deposited on the monolithic substrate, such that it contacts the exposed gate electrodes of the selected portion of the complementary metal oxide semiconductor devices. A top electrode material layer is deposited on the monolithic substrate, such that the top electrode material layer contacts the capacitive material layer in a region overlying the exposed gate electrodes of the selected portion of the complementary metal oxide semiconductor devices. The top electrode material layer and the capacitive material layer are removed to substantially the level of the upper surface of the protective material layer, thereby leaving the top electrode layer and the capacitive material layer overlying the gate electrodes for the selected portion of the complementary metal oxide semiconductor devices. In this manner, capacitors are formed from the top electrode material layer, the capacitive material layer, and the gate electrodes of the selected portion of the complementary metal oxide semiconductor devices.

US Patent:

6348413, Feb 19, 2002

Filed:

Sep 21, 1998

Appl. No.:

09/157855

Inventors:

Timothy Z. Hossain - Austin TX
Charles E. May - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2144

US Classification:

438682, 438680, 438683, 257770, 257773

Abstract:

In one aspect of the present invention, a method of forming a layer of silicide on a surface of a silicon-containing structure surface that is separated from a first structure by a second structure is provided. The method includes the steps of forming a layer of silicide-forming material on the surface of the silicon-containing structure, and the first and second structures. The layer of silicide-forming material is annealed in an ambient containing a nitrogen bearing species at a pressure greater than about one atmosphere to form the layer of silicide on the surface of the silicon-containing structure. The nitrogen bearing species reacts with the silicide-forming material to retard the formation of silicide on the third structure. The method reduces the potential for silicide bridging between, for example, the gate and source/drain regions of a transistor during silicide contact formation.

US Patent:

6362510, Mar 26, 2002

Filed:

Dec 7, 1998

Appl. No.:

09/206550

Inventors:

Mark I. Gardner - Cedar Creek TX
Charles E. May - Gresham OR

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2976

US Classification:

257374, 257602, 257610, 257647

Abstract:

A method for fabricating an integrated circuit is presented wherein a semiconductor substrate is provided having a dielectric layer formed on its upper surface. A groove is formed in the dielectric layer that extends from the upper surface of the semiconductor substrate to the upper surface of the dielectric layer. A silicon epitaxial layer is then grown within the groove. Barrier atoms are incorporated into the silicon epitaxial layer concurrently with the epitaxial growth process.

US Patent:

6403445, Jun 11, 2002

Filed:

Apr 6, 1999

Appl. No.:

09/286729

Inventors:

Mark I. Gardner - Cedar Creek TX
Frederick N. Hause - Austin TX
Charles E. May - Gresham OR

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21762

US Classification:

438424, 438221, 438432, 438764

Abstract:

An improved method of trench isolation formation includes, for one embodiment, applying a polysilicon layer above a planarized trench, and converting the polysilicon to oxide prior to etching the active areas. This converted oxide is denser than the materials usually used to fill the trench, such as TEOS, and results in less over-etching of the trench isolation region. The quality of the dielectric isolation is consequently improved, and in particular, less leakage current flows across the trench isolation region. Moreover, less leakage current flows from a subsequently formed local interconnect layer.

US Patent:

6410967, Jun 25, 2002

Filed:

Oct 15, 1998

Appl. No.:

09/173273

Inventors:

Frederick N. Hause - Austin TX
Mark I. Gardner - Cedar Creek TX
Charles E. May - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2972

US Classification:

257377, 257382, 257384, 257396, 257408, 257412, 257413

Abstract:

A transistor and a method for making a transistor are described. A metal layer is formed upon a semiconductor substrate, and a masking layer is formed upon the metal layer. The masking layer is patterned to form an opening therein, and portions of the metal layer not covered by the masking layer are removed. A gate dielectric layer is formed within the opening upon the semiconductor substrate; in an embodiment, spacers are also formed upon opposed sidewall surfaces of the masking layer. A conductive material is then deposited upon the dielectric material to form a gate conductor. The masking material is then removed, source and drain and lightly doped drain impurity areas are formed in the semiconductor substrate, and the metal layer is annealed to form a silicide in close proximity to the channel region. By depositing the metal layer prior to forming the gate conductor, the process described herein allows formation of a metal silicide adjacent or in close proximity to the channel region of the transistor. The process also allows formation of a metal gate conductor self-aligned with lightly doped drain or source-drain impurity areas.

US Patent:

6420220, Jul 16, 2002

Filed:

Apr 16, 1999

Appl. No.:

09/292913

Inventors:

Mark I. Gardner - Cedar Creek TX
H. Jim Fulford - Austin TX
Charles E. May - Gresham OR

Assignee:

Advanced Micro Devices, Inc. - Austin TX

International Classification:

H01L 2100

US Classification:

438151

Abstract:

A method is provided for fabricating a semiconductor device, the method including forming a dielectric layer above a structure, forming a silicidable layer above the dielectric layer and forming a conductive layer above the silicidable layer. The method also includes forming a silicided layer by siliciding a portion of the conductive layer using at least a portion of the silicidable layer and forming a gate conductor having sides by patterning the silicided layer and the conductive layer.

US Patent:

6432812, Aug 13, 2002

Filed:

Jul 16, 2001

Appl. No.:

09/906331

Inventors:

Charles E. May - Gresham OR

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 214763

US Classification:

438619, 438666, 438669, 438673, 438720

Abstract:

A method for reducing the coupling capacitance between adjacent electrically conductive interconnect lines of an integrated circuit. An electrically conductive layer is deposited and etched to produce electrically conductive interconnect lines having negatively sloped sidewalls. An insulating layer is deposited on the electrically conductive interconnect lines using a directional deposition to create a void between and directly adjacent electrically conductive interconnect lines. The void has a substantially lower dielectric constant than the material of the insulating layer, which reduces the coupling capacitance between adjacent electrically conductive interconnect lines.

US Patent:

6451657, Sep 17, 2002

Filed:

Feb 8, 2001

Appl. No.:

09/781044

Inventors:

Mark I. Gardner - Cedar Creek TX
Charles E. May - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21336

US Classification:

438299, 438199, 438528, 438585

Abstract:

A process is disclosed for fabricating a transistor having a channel length that is smaller than lengths resolvable using common photolithography techniques. A gate oxide layer is formed over a lightly doped semiconductor substrate. A gate conductor layer is then deposited over the gate oxide layer. The upper surface of the gate conductor layer includes a future conductor area laterally bounded by a spaced pair of target areas, wherein the lateral distance between the spaced pair of target areas is preferably chosen at the photolithography threshold. Nitrogen is implanted into the spaced pair of target areas to form a spaced pair of nitrogen bearing regions within the gate conductor layer, thereby defining a nitrogen free region in the gate conductor layer. A thermal anneal reduces the width of the nitrogen free region. A variable thickness oxide layer is then grown over the entire semiconductor topography and anisotropically etched to form an oxide mask over the reduced-width nitrogen free region.