Charles E Patton

US Patent:

6924808, Aug 2, 2005

Filed:

Mar 12, 2003

Appl. No.:

10/387338

Inventors:

Steven M. Kurihara - Palo Alto CA, US
Charles F. Patton - Dublin CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06T001/20

US Classification:

345506, 345503, 345531, 345533, 345564, 345613, 345614

Abstract:

A circuit for outputting area pattern bits from an area pattern array. The circuit includes a first stage, second stage and third stage. The first stage is configured to output N adjacent scan lines from a 2N×2N area pattern array based on a first address. N is a positive integer. The second stage is configured to receive the N adjacent scanlines and to select an N×N block from the N adjacent scanlines based on a second address. The third stage is configured to (a) select an (N/2)×N region of bits from the N×N block and load bits of the (N/2)×N region into a set of pixel tag outputs in a first mode, and (b) select an N×(N/2) region of bits from the N×N block and load bits of the N×(N/2) region into the set of pixel tag outputs in a second mode.

US Patent:

7310103, Dec 18, 2007

Filed:

Mar 5, 2002

Appl. No.:

10/091176

Inventors:

Charles Patton - Dublin CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G09G 5/00
G06T 15/40

US Classification:

345620, 345622, 345623, 345624, 345628, 345619, 345421

Abstract:

A system and method for performing viewport clipping for multiple viewports using a pipeline. The pixel address coordinates are compared against boundaries of a first viewport window. The results of this comparison, along with the pixel address coordinates, are registered and passed on to the next pipeline stage. There, the pixel address coordinates are compared against the boundaries of a second viewport window. The comparison results are combined with those passed from the previous stage, and the results are again registered. This scheme is repeated until the pixel has been tested against all the viewport window boundaries, with the intermediate results being combined into a single result indicative of whether the pixel is to be passed to the subsequent stages of the graphics pipeline or clipped.

US Patent:

7683303, Mar 23, 2010

Filed:

Jan 17, 2006

Appl. No.:

11/333989

Inventors:

Patrick Denis Lincoln - Woodside CA, US
Charles M. Patton - Eugene OR, US

Assignee:

SRI International - Menlo Park CA

International Classification:

H01L 27/00

US Classification:

2502081, 250214 R

Abstract:

The invention provides an imaging device comprised of nanoscale crossbar arrays upon a transmissive medium. The preferred embodiment employs a BOPET film as the transparent material bearing addressable nanoscale arrays, and the arrays connected to leads through micro lithographic techniques, and in turn connected to a logic device. An imaging volume is provided by stacking the array-bearing sheets. The volumetric imaging device functions omnidirectionally. By means of applying Fourier and/or geometric optics techniques to imaging data, various focal points and planes of focus can be calculated. The preferred embodiment is on the order of 1 cubic mm. Alternate embodiments include display and projection devices.

US Patent:

20130316322, Nov 28, 2013

Filed:

May 22, 2012

Appl. No.:

13/477938

Inventors:

Jeremy Roschelle - Palo Alto CA, US
Sarah Zaner - Lafayette CA, US
Charles M. Patton - Eugene OR, US

International Classification:

G09B 5/00

US Classification:

434350

Abstract:

The present disclosure relates to a method and apparatus for providing collaborative learning. In one embodiment, a method includes presenting a visual representation of a task in a first modality to a plurality of users in a group on a shared display and receiving a plurality of inputs from input devices associated with the respective users for solving the task. At least one of the inputs comprises a visual representation of the at least one input in a second modality that is different from the first modality and a successful completion of the task by the group requires a correct solution that is collectively dependent upon all of the inputs.

US Patent:

20130316323, Nov 28, 2013

Filed:

May 22, 2012

Appl. No.:

13/477952

Inventors:

JEREMY ROSCHELLE - Palo Alto CA, US
Sarah Zaner - Lafayette CA, US
Charles M. Patton - Eugene OR, US

International Classification:

G09B 5/00

US Classification:

434350

Abstract:

The present disclosure relates to methods and systems for providing collaborative learning. In one embodiment, a method includes presenting a first task to a plurality of users on a shared display and receiving inputs via respective input devices for collectively solving the task. The received inputs are analyzed to determine whether the task is correctly performed and to infer one or more probabilistic conclusions about a level of comprehension associated with the first task. An output is presented based upon the probabilistic conclusions about the level of comprehension.

US Patent:

48602493, Aug 22, 1989

Filed:

Oct 4, 1985

Appl. No.:

6/784922

Inventors:

Mark C. Nicely - Mountain View CA
Robert Schreiber - Palo Alto CA
Terry M. Parks - Sunnyvale CA
A. Joel Mannion - Sunnyvale CA
Gary R. Lang - Saratoga CA
Charles F. Patton - Milpitas CA

Assignee:

Saxpy Computer Corporation - Sunnyvale CA

International Classification:

G06F 1500
G06F 1516
G06F 1531
G06F 1300

US Classification:

364900

Abstract:

A reconfigurable processor array (RPA) for performing high speed operations on data arrays and eliminating I/O bottleneck. The array memory has a working side for storing arrays to be processed during a given array operation, and an I/O side for loading an array to be used during a subsequent operation and downloading an array resulting from a preceding operation.