Chau T Tran

US Patent:

8572302, Oct 29, 2013

Filed:

Oct 15, 2007

Appl. No.:

11/872673

Inventors:

Theodore White - Rancho Santa Margarita CA, US
Stanley Cheong - Lake Forest CA, US
Lim Hudiono - Laguna Niguel CA, US
William Dennin, III - Mission Viejo CA, US
Chau Tran - Huntington Beach CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

G06F 13/00

US Classification:

710 72

Abstract:

A controller and a method for interfacing between a host and storage medium. A storage medium interface includes CH0 circuitry for performing a CH0 process to access a buffer memory on behalf of the storage medium. A host interface includes CH1 circuitry for performing a CH1 process to access the buffer memory on behalf of the host. Access to the buffer memory is arbitrated in sequential tenures to each channel of the multi-channel bus within a maximum arbitration round trip time defined by the time taken by the storage medium to move a distance corresponding to N sectors in which N is greater than one. In the CH0 tenure, the CH0 process transfers data corresponding to N sectors of the storage medium in a multi-sector burst. The length of the tenure of the CH0 channel is pre-designated so that the multi-sector burst is completed within the CH0 tenure.