Chau M Tran

US Patent:

6483382, Nov 19, 2002

Filed:

Sep 15, 2000

Appl. No.:

09/663751

Inventors:

Moshe Gerstenhaber - Newton MA
Chau C. Tran - Malden MA
Mark Fazio - Winchester MA

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03F 345

US Classification:

330252, 330257

Abstract:

A current compensation circuit for an amplifier, for example an operational amplifier, having input and output stages coupled at a high-impedance node, compensates for any modulation of current occurring at the high-impedance node. Particularly, the compensation circuit of the present invention reduces the error current at the high-impedance node resulting from a mismatch in beta between PNP and NPN transistors in the output stage, and reduces any error current resulting from the Early voltage effects of transistors in the output stage. In this manner, the present invention serves to substantially isolate the amplifier input stage from the output load, and from any beta mismatch or Early voltage effects in the transistors of the output stage, resulting in greatly improved open-loop gain.

US Patent:

6549070, Apr 15, 2003

Filed:

Aug 21, 2000

Appl. No.:

09/642964

Inventors:

Chau C. Tran - Malden MA
Adrian Paul Brokaw - Burlington MA

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03F 345

US Classification:

330252, 330257, 330259, 330260, 330261

Abstract:

A high gain amplifier includes an intermediate gain stage; an output gain stage driven by the intermediate gain stage; an input stage, for driving the intermediate gain stage, which is balanced between positive and negative feedback in normal operation; bias means for driving the input stage to maintain balance between positive and negative feedback in normal operation; and a resistance for limiting the output current of the intermediate stage in response to the input stage being overdriven into positive feedback.

US Patent:

6876070, Apr 5, 2005

Filed:

Oct 4, 2000

Appl. No.:

09/679658

Inventors:

Moshe Gerstenhaber - Newton MA, US
Chau C. Tran - Malden MA, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H01L023/02
H01I023/48

US Classification:

257678, 257697

Abstract:

A repatterned integrated circuit chip package which balances and/or reduces the package capacitance associated with the gain resistor terminals to reduce the degradation of common mode rejection with frequency.

US Patent:

7208930, Apr 24, 2007

Filed:

Jan 10, 2005

Appl. No.:

11/033058

Inventors:

Chau C. Tran - Malden MA, US
A. Paul Brokaw - Tucson AZ, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

G05F 3/16

US Classification:

323314, 323907

Abstract:

A bandgap voltage regulator is arranged such that, when a desired output voltage is present between its output and common terminals, current densities in a pair of bipolar transistors having unequal emitter areas are maintained in a fixed ratio. The difference in the transistors' base-emitter voltages is across a resistor, which thus conducts a PTAT current. The regulator also generates a CTAT current, and both the PTAT and CTAT currents are made to flow in another resistor, with the resulting voltages added by superposition. The regulator's resistors are sized such that Vis an integral or fractional multiple of V, where Vis the bandgap voltage for the fabrication process used to make the regulator's transistors, such that Vis temperature invariant, to a first order. The resistors are preferably realized using unit resistors having a predetermined resistance, or series and/or parallel combinations of unit resistors.

US Patent:

7265615, Sep 4, 2007

Filed:

Jun 30, 2005

Appl. No.:

11/172186

Inventors:

Alasdair G. Alexander - Andover MA, US
Chau C. Tran - Malden MA, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03F 3/45

US Classification:

330 69, 330 9

Abstract:

A multiple differential amplifier system and method for transconductance mismatch compensation which in a first phase connects to a differential switched input of a null amplifier, the differential signal input of the main amplifier, inverted, for compensating for offset errors and transconductance mismatches in the null amplifier; and storing in a null storage device connected to an auxiliary input of the null amplifier the output of the null amplifier representing the compensation for the offset error and transconductance mismatch of the null amplifier; and in a second phase connecting the differential switched input of the null amplifier to the differential feedback input of the main amplifier and storing in the main storage device connected to an auxiliary input of the main amplifier the output of the null amplifier representing the compensation for the main amplifier offset error and transconductance mismatch.

US Patent:

7436052, Oct 14, 2008

Filed:

Feb 28, 2005

Appl. No.:

11/067795

Inventors:

Moshe Gerstenhaber - Newton MA, US
Chau C. Tran - Malden MA, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H01L 23/02

US Classification:

257678, 257697, 257E27016

Abstract:

A repatterned integrated circuit chip package which balances and/or reduces the package capacitance associated with the gain resistor terminals to reduce the degradation of common mode rejection with frequency.

US Patent:

7495426, Feb 24, 2009

Filed:

Mar 6, 2006

Appl. No.:

11/370155

Inventors:

Chau C. Tran - Malden MA, US
A. Paul Brokaw - Tucson AZ, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

G05F 3/16

US Classification:

323315, 323907

Abstract:

A temperature setpoint circuit comprises bipolar transistors Q and Q which receive currents I and I at their respective collectors and are operated at unequal current densities, with a resistance R connected between their bases such that the difference in their base-emitter voltages (ΔV) appears across R. An additional PTAT current I is maintained in a constant ratio to I and I and provided to the collector of Q while Q is off, and is not provided while Q is on. The circuit is arranged such that Q is turned on and conducts a current equal to Ia when:ΔV=(kT/q)ln(NI/Ia), where Ia=I+I, the temperature T at which ΔV=(kT/q)ln(NI/Ia) being the circuit's setpoint temperature, such that the switching of current I provides hysteresis for the setpoint temperature which is approximately constant over temperature.

US Patent:

8536923, Sep 17, 2013

Filed:

Jul 21, 2011

Appl. No.:

13/188426

Inventors:

Moshe Gerstenhaber - Newton MA, US
Sandro Herrera - Medford MA, US
Chau Cuong Tran - Malden MA, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03L 5/00

US Classification:

327307, 327317, 330 9

Abstract:

A system and method for reducing gain error and distortion in an operational amplifier due to errors in the second or integrator stage. A correction circuit may replicate an error current and insert the current into the signal stream to preempt the induction of an error at the amplifier's input. A capacitor may sample the error voltage at the input of the integrator stage of the amplifier and generate a replica of the error current in the integration capacitor to feed it into the input of the integrator stage. This eliminates any nonlinearity errors created by error currents in the compensation or integration capacitor at the second or integrator stage of the two-stage amplifier. Feeding the error current to the integrator stage may be facilitated with a unity gain buffer and a current mirror.