Chen Zhang

US Patent:

20210273077, Sep 2, 2021

Filed:

Feb 28, 2020

Appl. No.:

16/805346

Inventors:

- Armonk NY, US
Chun-Chen Yeh - Danbury CT, US
Alexander Reznicek - Troy NY, US
Chen Zhang - Albany NY, US

International Classification:

H01L 29/66
H01L 21/8238
H01L 29/78
H01L 29/16
H01L 29/08
H01L 29/417

Abstract:

A semiconductor structure, and a method for forming the same includes an amorphous semiconductor layer in contact with a top surface of a channel fin extending vertically from a bottom source/drain located above a substrate. A hard mask memorization layer is formed directly above the amorphous semiconductor layer, portions of the amorphous semiconductor layer in contact with the top surface of the channel fin are recrystallized forming recrystallized regions. The amorphous semiconductor layer is selective removed and a second dielectric layer is deposited to form a top spacer. The hard mask memorization layer and the recrystallized regions are removed, and a first epitaxial region is formed above the channel fin followed by a second epitaxial region positioned above the first epitaxial region and between the second dielectric layer forming a top source/drain of the semiconductor structure.

US Patent:

20200365469, Nov 19, 2020

Filed:

Aug 3, 2020

Appl. No.:

16/983587

Inventors:

- Armonk NY, US
Takashi Ando - Tuckahoe NY, US
Oleg Gluschenkov - Tannersville NY, US
Chen Zhang - Guilderland NY, US
Koji Watanabe - Rensselaer NY, US

International Classification:

H01L 21/8238
H01L 29/49
H01L 29/786
H01L 27/092
H01L 21/265
H01L 21/762
H01L 21/324
H01L 21/308

Abstract:

A method of forming a semiconductor structure includes forming one or more vertical fins each including a first semiconductor layer providing a vertical transport channel for a lower vertical transport field-effect transistor (VTFET) of a stacked VTFET structure, an isolation layer over the first semiconductor layer, and a second semiconductor layer over the isolation layer providing a vertical transport channel for an upper VTFET of the stacked VTFET structure. The method also includes forming a first gate stack including a first gate dielectric layer and a first gate conductor layer surrounding a portion of the first semiconductor layer of the vertical fins. The method further includes forming a second gate stack including a second gate dielectric layer and a second gate conductor layer surrounding a portion of the second semiconductor layer of the vertical fins. The first gate conductor layer and the second gate conductor layer are the same material.

US Patent:

20200328127, Oct 15, 2020

Filed:

Apr 15, 2019

Appl. No.:

16/384545

Inventors:

- Armonk NY, US
Takashi Ando - Tuckahoe NY, US
Oleg Gluschenkov - Tannersville NY, US
Chen Zhang - Guilderland NY, US
Koji Watanabe - Rensselaer NY, US

International Classification:

H01L 21/8238
H01L 21/324
H01L 21/308
H01L 21/762
H01L 21/265
H01L 27/092
H01L 29/786
H01L 29/49

Abstract:

A method of forming a semiconductor structure includes forming one or more vertical fins each including a first semiconductor layer providing a vertical transport channel for a lower vertical transport field-effect transistor (VTFET) of a stacked VTFET structure, an isolation layer over the first semiconductor layer, and a second semiconductor layer over the isolation layer providing a vertical transport channel for an upper VTFET of the stacked VTFET structure. The method also includes forming a first gate stack including a first gate dielectric layer and a first gate conductor layer surrounding a portion of the first semiconductor layer of the vertical fins. The method further includes forming a second gate stack including a second gate dielectric layer and a second gate conductor layer surrounding a portion of the second semiconductor layer of the vertical fins. The first gate conductor layer and the second gate conductor layer are the same material.