Chen Zhang

US Patent:

20220415790, Dec 29, 2022

Filed:

Jun 24, 2021

Appl. No.:

17/304674

Inventors:

- Armonk NY, US
Chen Zhang - Guilderland NY, US
Brent Anderson - Jericho VT, US
Nicholas Anthony Lanzillo - Wynantskill NY, US

International Classification:

H01L 23/528
H01L 23/522
H01L 21/768
H01L 21/311

Abstract:

A top via interconnect with enlarged via top and a fabrication method therefor. One embodiment may comprise a semiconductor interconnect structure, comprising a first dielectric layer having a top surface, a bottom metal line formed in the dielectric layer, a second dielectric layer deposited above the top surface of the first dielectric layer, a via etched through the second dielectric layer above the bottom metal line, wherein the via exposes at least a portion of the top surface of the first dielectric layer, and a metal stud in the via that extends over the exposed at least a portion of the first dielectric layer. The metal stud in the via may further comprise a shoulder surface and a convex top surface.

US Patent:

20220406908, Dec 22, 2022

Filed:

Jun 22, 2021

Appl. No.:

17/304461

Inventors:

- ARMONK NY, US
Ruilong Xie - Niskayuna NY, US
Chen Zhang - Guilderland NY, US
Kangguo Cheng - Schenectady NY, US

International Classification:

H01L 29/417
H01L 29/40
H01L 29/06
H01L 29/423

Abstract:

A stacked semiconductor device comprising a lower source/drain epi located on top of a bottom dielectric layer. An isolation layer located on top of the lower source/drain epi and an upper source/drain epi located on top of the isolation layer. A lower electrical contact that is connected to the lower source/drain epi, wherein the lower electrical contact is in direct contact with multiple side surfaces of the lower source/drain epi.

US Patent:

20220392797, Dec 8, 2022

Filed:

Jun 8, 2021

Appl. No.:

17/341640

Inventors:

- Armonk NY, US
Chen Zhang - Guilderland NY, US
HUIMEI ZHOU - Albany NY, US
Ruilong Xie - Niskayuna NY, US

International Classification:

H01L 21/74
H01L 21/8234
H01L 27/088
H01L 23/535

Abstract:

An approach for creating a buried local interconnect around a DDB (double diffusion break) to reduce parasitic capacitance on a semiconductor device is disclosed. The approach utilizes a metal, as the local interconnect, buried in a cavity around the DDB region of a semiconductor substrate. The metal is disposed by two dielectric layers and the substrate. The two dielectric layers are recessed beneath two gate spacers. The buried local interconnect is recessed into the cavity where the top surface of the interconnect is situated below the top surface of the surrounding S/D (source/drain) epi (epitaxy). The metal of the local interconnect can be made from W, Ru or Co.

US Patent:

20220199776, Jun 23, 2022

Filed:

Dec 17, 2020

Appl. No.:

17/125850

Inventors:

- Armonk NY, US
Ruilong Xie - Niskayuna NY, US
Chen Zhang - Guilderland NY, US
Ekmini Anuja De Silva - Slingerlands NY, US

International Classification:

H01L 29/10
H01L 21/308
H01L 29/78

Abstract:

A semiconductor structure, and a method of making the same, includes a semiconductor substrate having an uppermost surface and a fin structure on the uppermost surface of the semiconductor substrate including n first regions extending perpendicular to the uppermost surface of the semiconductor substrate and n−1 second regions extending between and connecting each of the n first regions and parallel to the uppermost surface of the semiconductor substrate, wherein n≥3.

US Patent:

20230116251, Apr 13, 2023

Filed:

Sep 29, 2021

Appl. No.:

17/489029

Inventors:

- Armonk NY, US
Alexander Reznicek - Troy NY, US
Ruilong Xie - Niskayuna NY, US
Julien Frougier - Albany NY, US
Chen Zhang - Guilderland NY, US

International Classification:

G06N 3/063

Abstract:

A semiconductor structure is provided. The semiconductor device includes a magnetic layer located between a first electrode and a second electrode formed on a substrate. The semiconductor device further includes a first write element electrically coupled to the magnetic layer adjacent to the first electrode. The semiconductor device also includes a second write element electrically coupled to the magnetic layer adjacent to the second electrode. The semiconductor device additionally includes a plurality of read elements electrically coupled to the magnetic layer located between the first write element and the second write element.

US Patent:

20230104456, Apr 6, 2023

Filed:

Oct 6, 2021

Appl. No.:

17/450121

Inventors:

- Armonk NY, US
Junli WANG - Slingerlands NY, US
Indira SESHADRI - Niskayuna NY, US
Chen ZHANG - Guilderland NY, US
Ruilong XIE - Niskayuna NY, US
Joshua M. RUBIN - Albany NY, US
Hemanth JAGANNATHAN - Niskayuna NY, US

International Classification:

H01L 29/66
H01L 29/78
H01L 27/092
H01L 21/8238
H01L 21/8234

Abstract:

An apparatus includes a fin, a gate, and a gate contact. A portion of the fin is disposed in a first layer. The gate is disposed in the first layer and adjacent to the fin. The gate contact is disposed on the gate and in a second layer, wherein the second layer is disposed on the first layer such that the gate contact is above the fin.

US Patent:

20230086967, Mar 23, 2023

Filed:

Sep 22, 2021

Appl. No.:

17/481647

Inventors:

- Armonk NY, US
SOMNATH GHOSH - CLIFTON PARK NY, US
Chen Zhang - Guilderland NY, US
Junli Wang - Slingerlands NY, US
Devendra K. Sadana - Pleasantville NY, US
Dechao Guo - Niskayuna NY, US

International Classification:

H01L 29/78
H01L 29/08
H01L 25/07

Abstract:

A semiconductor device fabrication method is provided. The semiconductor device fabrication method includes frontside semiconductor device processing on a frontside of a wafer, flipping the wafer, backside semiconductor device processing on a backside of the wafer and backside and frontside contact formation processing on the backside and frontside of the wafer, respectively.

US Patent:

20230073990, Mar 9, 2023

Filed:

Aug 25, 2021

Appl. No.:

17/445832

Inventors:

- Armonk NY, US
Ruilong Xie - Niskayuna NY, US
Alexander Reznicek - Troy NY, US
Chen Zhang - Guilderland NY, US

International Classification:

H01L 29/78
H01L 29/06
H01L 29/66

Abstract:

Embodiments of the invention include a vertical field-effect transistor (VTFET) inverter. The VTFET inverter may include a p-channel field-effect transistor (P-FET) with a P-FET top source/drain and a P-FET bottom source/drain. The VTFET inverter may also include an n-channel field-effect transistor (N-FET) comprising an N-FET top source/drain and a N-FET bottom source/drain. The VTFET inverter may also include a buried contact located at a boundary between the P-FET bottom source/drain and the N-FET bottom source/drain. The VTFET inverter may also include a Vout contact electrically connected to one of the P-FET bottom source/drain and the N-FET bottom source/drain.