Chen A Zhang

US Patent:

20130329876, Dec 12, 2013

Filed:

Jun 8, 2012

Appl. No.:

13/491666

Inventors:

Nancy Ellen Kho - Belmont MA, US
Chen Zhang - Waltham MA, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H04M 1/56

US Classification:

37914204

Abstract:

Described are a system and method for processing content in a unified communications environment. As part of an electronic communication session between a first party electronic device and at least one second party electronic device, an identifier is received from the first party electronic device at the at least one second party electronic device. A search is performed for collaborative history data at the second party electronic device using the identifier. Data related to the electronic communication session and/or the collaborative history data is presented at the second party electronic device.

US Patent:

20130332536, Dec 12, 2013

Filed:

May 3, 2013

Appl. No.:

13/886443

Inventors:

International Business Machines Corporation - , US
Chen Zhang - Waltham MA, US

Assignee:

International Business Machines Corporation - Armonk MA

International Classification:

H04L 29/06

US Classification:

709205

Abstract:

Described are a system and method for processing content in a unified communications environment. As part of an electronic communication session between a first party electronic device and at least one second party electronic device, an identifier is received from the first party electronic device at the at least one second party electronic device. A search is performed for collaborative history data at the second party electronic device using the identifier. Data related to the electronic communication session and/or the collaborative history data is presented at the second party electronic device.

US Patent:

20200365469, Nov 19, 2020

Filed:

Aug 3, 2020

Appl. No.:

16/983587

Inventors:

- Armonk NY, US
Takashi Ando - Tuckahoe NY, US
Oleg Gluschenkov - Tannersville NY, US
Chen Zhang - Guilderland NY, US
Koji Watanabe - Rensselaer NY, US

International Classification:

H01L 21/8238
H01L 29/49
H01L 29/786
H01L 27/092
H01L 21/265
H01L 21/762
H01L 21/324
H01L 21/308

Abstract:

A method of forming a semiconductor structure includes forming one or more vertical fins each including a first semiconductor layer providing a vertical transport channel for a lower vertical transport field-effect transistor (VTFET) of a stacked VTFET structure, an isolation layer over the first semiconductor layer, and a second semiconductor layer over the isolation layer providing a vertical transport channel for an upper VTFET of the stacked VTFET structure. The method also includes forming a first gate stack including a first gate dielectric layer and a first gate conductor layer surrounding a portion of the first semiconductor layer of the vertical fins. The method further includes forming a second gate stack including a second gate dielectric layer and a second gate conductor layer surrounding a portion of the second semiconductor layer of the vertical fins. The first gate conductor layer and the second gate conductor layer are the same material.

US Patent:

20200328127, Oct 15, 2020

Filed:

Apr 15, 2019

Appl. No.:

16/384545

Inventors:

- Armonk NY, US
Takashi Ando - Tuckahoe NY, US
Oleg Gluschenkov - Tannersville NY, US
Chen Zhang - Guilderland NY, US
Koji Watanabe - Rensselaer NY, US

International Classification:

H01L 21/8238
H01L 21/324
H01L 21/308
H01L 21/762
H01L 21/265
H01L 27/092
H01L 29/786
H01L 29/49

Abstract:

A method of forming a semiconductor structure includes forming one or more vertical fins each including a first semiconductor layer providing a vertical transport channel for a lower vertical transport field-effect transistor (VTFET) of a stacked VTFET structure, an isolation layer over the first semiconductor layer, and a second semiconductor layer over the isolation layer providing a vertical transport channel for an upper VTFET of the stacked VTFET structure. The method also includes forming a first gate stack including a first gate dielectric layer and a first gate conductor layer surrounding a portion of the first semiconductor layer of the vertical fins. The method further includes forming a second gate stack including a second gate dielectric layer and a second gate conductor layer surrounding a portion of the second semiconductor layer of the vertical fins. The first gate conductor layer and the second gate conductor layer are the same material.