Cheng Hsueh Hsieh

US Patent:

7872495, Jan 18, 2011

Filed:

Jan 28, 2010

Appl. No.:

12/695992

Inventors:

Toan D. Tran - San Jose CA, US
Cheng H. Hsieh - Los Gatos CA, US
Mark J. Marlett - Livermore CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 19/003

US Classification:

326 30, 326 34

Abstract:

A unit cell for a programmable termination circuit in an integrated circuit and a method for programming such termination circuit are described. In an embodiment, such unit cells may have three n-type and three p-type transistors. A first transistor is coupled to receive a first float control signal. A second transistor is coupled to receive a second float control signal. The third and fourth transistors are coupled to receive a first termination voltage control signal. The fifth and sixth transistors are coupled to receive a second termination voltage control signal. The first float control signal and the second float control signal are a pair of complementary signals.

US Patent:

8184029, May 22, 2012

Filed:

Jun 16, 2010

Appl. No.:

12/817111

Inventors:

Cheng Hsiang Hsieh - Los Gatos CA, US
Mengchi Liu - Fremont CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03M 1/66

US Classification:

341144, 327231, 341136

Abstract:

A phase interpolator is described. The phase interpolator can have a code-to-bias converter, and a phase interpolation interface. In an embodiment of a code-to-bias converter, a single digital-to-analog converter is provided to generate bias signaling associated with phase signals. A bleeder current source is provided to generate a bleeder current, where the bleeder current is selected responsive to phase so the phase signals do not reach zero current.

US Patent:

8253451, Aug 28, 2012

Filed:

Jun 16, 2010

Appl. No.:

12/817126

Inventors:

Cheng Hsiang Hsieh - Los Gatos CA, US
Mengchi Liu - Fremont CA, US
Yu Xu - Palo Alto CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03L 7/00

US Classification:

327141, 327157, 327161

Abstract:

A clock data recovery module and a method of operation thereof are described. In an embodiment, a data stream is received. Transitions in the data stream are detected to provide phase signaling for indicating phase relationships to the transitions detected. A lock detector receives the phase signaling. The lock detector accumulates phase information from the phase signaling and temporarily stores an accumulated total of the phase information representative of a code change, and the lock detector determines whether the code change is within a set range over a time period and resets the accumulated total at a conclusion of the time period.

US Patent:

8549057, Oct 1, 2013

Filed:

Oct 4, 2010

Appl. No.:

12/897671

Inventors:

Cheng Hsiang Hsieh - Los Gatos CA, US
Arif Akram Siddiqi - Santa Clara CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 17/10
H03H 7/30

US Classification:

708319, 708322, 375232

Abstract:

An embodiment of a method for control of signal level is disclosed. In such an embodiment, a number for a pre-cursor set, a number for a cursor set, and a number for a post-cursor set are set corresponding to a weighted contribution of a pre-cursor symbol, a weighted contribution of a cursor symbol, and a weighted contribution of a post-cursor symbol, respectively, for the signal level. A number associated with a high-impedance set is determined. The number associated with the high-impedance set is determined by subtracting the number for the pre-cursor set, the number for the cursor set, and the number for the post-cursor set from a total available amount of units. The high-impedance set provides no weighted contribution to the signal level. Data is transmitted using the signal level set responsive to the pre-cursor set, the cursor set, and the post-cursor set.