Cheng Chieh Wu

US Patent:

6782886, Aug 31, 2004

Filed:

Mar 20, 2001

Appl. No.:

09/812988

Inventors:

Sharad Narayan - Sunnyvale CA
Yehuda Ivri - Irvine CA
Cheng H. Wu - Sunnyvale CA
Miro S. Cater - Daytona Beach FL

Assignee:

Aerogen, Inc. - Mountain View CA

International Classification:

A61M 1100

US Classification:

12820014, 12820312, 604 48, 604514, 604186, 604246

Abstract:

An apparatus to make a certain volume of liquid available for atomization comprises a container adapted to hold a liquid, and a piston pump. The piston pump comprises a piston member and a valve body, with the piston member being slidable within the valve body. Further, the valve body functions with the piston member to define a metering chamber. In this way, the metering chamber is adapted to be filled with liquid from the container when the piston member is moved to a filling position, and the piston pump is adapted to dispense a known volume of the liquid from the metering chamber when the piston member is moved to a dispensing position.

US Patent:

48309745, May 16, 1989

Filed:

Jan 11, 1988

Appl. No.:

7/142641

Inventors:

Chung-Chen Chang - Los Altos CA
Cheng C. Wu - San Jose CA

Assignee:

Atmel Corporation - San Jose CA

International Classification:

H01L 2996

US Classification:

437034

Abstract:

An EPROM fabrication process using CMOS N-well technology with a two polysilicon floating gate stack and a double layer of conductive lines providing a large process tolerance latitudes, a small reliable memory cell and high density. Channel stops and field oxide are formed by implanting boron ions, followed by a high temperature drive-in and oxidation cycle with a 1000-2500. ANG. thick nitride mask covering device areas. The floating gate stack is formed by forming a first gate oxide layer depositing a first polysilicon layer having a thickness of 2000-2600. ANG. , removing these layers from non-memory cell areas, growing a uniformly thick second oxide layer at 1100. degree. -1200. degree. C. over both the substrate and first polysilicon layer, depositing a second polysilicon gate layer and selectively etching away the layers to form first the device gates and second memory all gate from the second polysilicon layer, and then the floating gate from the first polysilicon layer using the second gate as a self-aligning mask. Metal coverage in the double layer of conductive lines is improved by rounding corners of glass and intermetal layers by means of glass reflow and planarization and wet/dry etching of the intermetal layer.

US Patent:

20210365391, Nov 25, 2021

Filed:

Aug 2, 2021

Appl. No.:

17/392192

Inventors:

- Boise ID, US
Ying Yu Tai - Mountain View CA, US
Cheng Yuan Wu - Fremont CA, US

International Classification:

G06F 13/16
G06F 13/42
G06F 11/07

Abstract:

An instruction can be received at a sequencer from a controller. The sequencer can be in a package including the sequencer and one or more memory components. The sequencer is operatively coupled to a controller that is separate from the package. A processing device of the sequencer can perform an operation based on the instruction on at least one of the one or more memory components in the package.

US Patent:

20210286665, Sep 16, 2021

Filed:

Jun 1, 2021

Appl. No.:

17/335433

Inventors:

- Boise ID, US
Ying Yu Tai - Mountain View CA, US
Cheng Yuan Wu - Fremont CA, US

International Classification:

G06F 11/07
G06F 13/12
G06F 13/16

Abstract:

A processing device can determine a configuration parameter based on a memory type of a memory component that is managed by a memory system controller. The processing device can receive data from a host system. The processing device can generate, by performing a memory operation using the configuration parameter, an instruction based on the data. The processing device can identify a sequencer of a plurality of sequencers that are collocated, within a single package external to the memory system controller, wherein each sequencer of the plurality of sequencers interfaces with a respective memory component. The processing device can send the instruction to the sequencer.

US Patent:

20210208820, Jul 8, 2021

Filed:

Mar 23, 2021

Appl. No.:

17/301044

Inventors:

- Boise ID, US
Cheng Yuan Wu - Fremont CA, US
Ying Yu Tai - Mountain View CA, US

International Classification:

G06F 3/06

Abstract:

A host operation to be performed can be received. Sub-operations that are associated with the received host operation can be determined. A memory component of multiple memory components can be identified for each sub-operation. Furthermore, each sub-operation can be transmitted to a media sequencer component that is associated with a respective memory component of the memory components.

US Patent:

20210073068, Mar 11, 2021

Filed:

Nov 20, 2020

Appl. No.:

17/100571

Inventors:

- Boise ID, US
Jiangli Zhu - San Jose CA, US
Ying Yu Tai - Mountain View CA, US
Ning Chen - San Jose CA, US
Zhengang Chen - San Jose CA, US
Cheng Yuan Wu - Fremont CA, US

International Classification:

G06F 11/07
G11C 29/52
G06F 11/10

Abstract:

A read operation to retrieve data stored at a memory device is performed. Whether the data retrieved from the memory device includes an error that is not correctable is determined. Responsive to determining that the data retrieved from the memory device comprises the error that is not correctable, a buffer in a data path along which a write operation was performed to write the data at the memory device is searched for the data.

US Patent:

20200089429, Mar 19, 2020

Filed:

Sep 14, 2018

Appl. No.:

16/132096

Inventors:

- Boise ID, US
Cheng Yuan Wu - Fremont CA, US
Ying Yu Tai - Mountain View CA, US

International Classification:

G06F 3/06

Abstract:

A host operation to be performed can be received. Sub-operations that are associated with the received host operation can be determined. A memory component of multiple memory components can be identified for each sub-operation. Furthermore, each sub-operation can be transmitted to a media sequencer component that is associated with a respective memory component of the memory components.

US Patent:

20200081763, Mar 12, 2020

Filed:

Sep 6, 2018

Appl. No.:

16/123900

Inventors:

- Boise ID, US
Ying Yu Tai - Mountain View CA, US
Cheng Yuan Wu - Fremont CA, US

International Classification:

G06F 11/07
G06F 13/16
G06F 13/12

Abstract:

A processing device can determine a configuration parameter to be used in an error correction code (ECC) operation. The configuration parameter is based on a memory type of a memory component that is associated with a controller. Data can be received from a host system. The processing device can generate a code word for the data by using the ECC operation that is based on the configuration parameter. The code word can be sent to a sequencer that is external to the controller.