Chi Hung Chan

US Patent:

7590137, Sep 15, 2009

Filed:

Nov 22, 2005

Appl. No.:

11/285708

Inventors:

Chi Bun Chan - Longmont CO, US
Jonathan B. Ballagh - Boulder CO, US
Nabeel Shirazi - San Jose CA, US

Assignee:

XILINX, Inc. - San Jose CA

International Classification:

H04J 3/24

US Classification:

370419, 370474, 710 20, 703 13

Abstract:

A network processor, disposed on an integrated circuit can include an ingress unit having a dual port block random access memory and an egress unit having a dual port block random access memory. The network processor further can include a network interface configured to write packetized data to the ingress unit and read packetized data from the egress unit as well as a coordination processor configured to coordinate movement of data between the network interface, the ingress unit, and the egress unit.

US Patent:

7636653, Dec 22, 2009

Filed:

Jan 31, 2006

Appl. No.:

11/343367

Inventors:

Chi Bun Chan - Longmont CO, US
Jonathan B. Ballagh - Boulder CO, US
Nabeel Shirazi - San Jose CA, US
Roger B. Milne - Boulder CO, US

Assignee:

XILINX, Inc. - San Jose CA

International Classification:

G06F 9/455
G06F 17/50

US Classification:

703 14, 703 22, 703 27

Abstract:

An Ethernet co-simulation interface for use with a software-based simulation tool and a design under test disposed on a programmable device can include a host interface and a network processor. The host interface can execute on a host computing system and facilitate data transfer between the software-based simulation tool and a communication link to the design under test. The network processor can be implemented within the programmable device and facilitate data transfer between the communication link and the design under test. The host interface and the network processor can exchange simulation data formatted as raw Ethernet frames over a point-to-point Ethernet connection.

US Patent:

7707019, Apr 27, 2010

Filed:

Sep 23, 2005

Appl. No.:

11/234529

Inventors:

Jonathan B. Ballagh - Boulder CO, US
Chi Bun Chan - Longmont CO, US
Nabeel Shirazi - San Jose CA, US
Roger B. Milne - Boulder CO, US

Assignee:

XILINX, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

703 13

Abstract:

A method of co-simulation involving a high level modeling system and an integrated circuit such as, e. g. , a programmable logic device (PLD) can include, when writing to at least one input port of the PLD, storing a plurality of commands from a co-simulation engine within a command buffer and, responsive to a send condition, sending the plurality of commands to the PLD as a single transaction. When reading from at least one output port of the PLD, selectively reading from a cache external to the PLD or a memory of the PLD according to a state of cache coherency.

US Patent:

7992111, Aug 2, 2011

Filed:

May 18, 2009

Appl. No.:

12/467678

Inventors:

Haibing Ma - Superior CO, US
Jingzhao Ou - Sunnyvale CA, US
Chi Bun Chan - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 9/45

US Classification:

716103, 716101, 716102, 716104, 716111, 716139

Abstract:

Approaches for processing an electronic circuit design. In one embodiment, the graphical model of an outer subsystem block and an inner subsystem block are translated into a high-level language (HLL) program. The HLL program includes a specification of a first function corresponding to the outer subsystem block and within the specification of the first function a specification of a second function corresponding to the inner subsystem block. The specification of the first function references a parameter of the outer subsystem block and specifies invocation of the second function. The specification of the second function specifies invocation of a third function corresponding to a leaf block in the inner subsystem block. The specification of the first function references a variable corresponding to the parameter, and that variable is referenced by the second or third functions. Execution of the HLL program instantiates a model of the design.

US Patent:

8352229, Jan 8, 2013

Filed:

Jan 26, 2009

Appl. No.:

12/359409

Inventors:

Haibing Ma - Superior CO, US
Chi Bun Chan - San Jose CA, US
Jingzhao Ou - Sunnyvale CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

703 13

Abstract:

A computer-implemented method of creating a simulation engine for simulating a circuit design can include receiving a source code contribution from a high level modeling system and receiving a simulation model specified in an interpretive language that specifies the circuit design. The source code contribution can be compiled together with the simulation model using a Just-In-Time compiler. A simulation engine, specified in native machine code, can be output as a single, integrated software component formed from the source code contribution and the simulation model.