Chi Bun Chan

US Patent:

7590137, Sep 15, 2009

Filed:

Nov 22, 2005

Appl. No.:

11/285708

Inventors:

Chi Bun Chan - Longmont CO, US
Jonathan B. Ballagh - Boulder CO, US
Nabeel Shirazi - San Jose CA, US

Assignee:

XILINX, Inc. - San Jose CA

International Classification:

H04J 3/24

US Classification:

370419, 370474, 710 20, 703 13

Abstract:

A network processor, disposed on an integrated circuit can include an ingress unit having a dual port block random access memory and an egress unit having a dual port block random access memory. The network processor further can include a network interface configured to write packetized data to the ingress unit and read packetized data from the egress unit as well as a coordination processor configured to coordinate movement of data between the network interface, the ingress unit, and the egress unit.

US Patent:

7636653, Dec 22, 2009

Filed:

Jan 31, 2006

Appl. No.:

11/343367

Inventors:

Chi Bun Chan - Longmont CO, US
Jonathan B. Ballagh - Boulder CO, US
Nabeel Shirazi - San Jose CA, US
Roger B. Milne - Boulder CO, US

Assignee:

XILINX, Inc. - San Jose CA

International Classification:

G06F 9/455
G06F 17/50

US Classification:

703 14, 703 22, 703 27

Abstract:

An Ethernet co-simulation interface for use with a software-based simulation tool and a design under test disposed on a programmable device can include a host interface and a network processor. The host interface can execute on a host computing system and facilitate data transfer between the software-based simulation tool and a communication link to the design under test. The network processor can be implemented within the programmable device and facilitate data transfer between the communication link and the design under test. The host interface and the network processor can exchange simulation data formatted as raw Ethernet frames over a point-to-point Ethernet connection.

US Patent:

7673201, Mar 2, 2010

Filed:

Mar 12, 2009

Appl. No.:

12/402728

Inventors:

Chi Bun Chan - San Jose CA, US
Jingzhao Ou - Sunnyvale CA, US

Assignee:

XILINX, Inc. - San Jose CA

International Classification:

G01R 31/28
G06F 7/38
H03K 19/00

US Classification:

714725, 714731, 326 40, 716 17

Abstract:

A method of restoring a selected operational state of a circuit design implemented within a programmable integrated circuit (IC) can include pipelining a clock gating signal that selectively pauses a clock of the circuit design, and storing configuration data specifying an operational state of the circuit design at a first simulation clock cycle in non-configuration memory. At a second simulation clock cycle, the clock of the circuit design can be gated. The stored configuration data can be loaded into configuration memory of the programmable IC, wherein loading the configuration data reconfigures the circuit design and restores the operational state of the circuit design in existence at the first simulation clock cycle. The clock of the circuit design can be advanced a number of clock cycles corresponding to a difference between the second simulation clock cycle and the first simulation clock cycle.

US Patent:

7707019, Apr 27, 2010

Filed:

Sep 23, 2005

Appl. No.:

11/234529

Inventors:

Jonathan B. Ballagh - Boulder CO, US
Chi Bun Chan - Longmont CO, US
Nabeel Shirazi - San Jose CA, US
Roger B. Milne - Boulder CO, US

Assignee:

XILINX, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

703 13

Abstract:

A method of co-simulation involving a high level modeling system and an integrated circuit such as, e. g. , a programmable logic device (PLD) can include, when writing to at least one input port of the PLD, storing a plurality of commands from a co-simulation engine within a command buffer and, responsive to a send condition, sending the plurality of commands to the PLD as a single transaction. When reading from at least one output port of the PLD, selectively reading from a cache external to the PLD or a memory of the PLD according to a state of cache coherency.

US Patent:

7746099, Jun 29, 2010

Filed:

Jan 11, 2008

Appl. No.:

12/008489

Inventors:

Chi Bun Chan - San Jose CA, US
Nabeel Shirazi - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 19/173

US Classification:

326 38, 326 8

Abstract:

A method of implementing a circuit in a device having programmable logic is disclosed. The method comprises implementing a circuit in the programmable logic of the device; storing data in a block of random access memory; performing a partial reconfiguration of the device, where new data is stored in the block of random access memory; and accessing the new data. A system of implementing a circuit in a device having programmable logic is also disclosed.

US Patent:

7747423, Jun 29, 2010

Filed:

Sep 27, 2006

Appl. No.:

11/527841

Inventors:

Nabeel Shirazi - San Jose CA, US
Jonathan B. Ballagh - Boulder CO, US
Chi Bun Chan - Longmont CO, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

703 13, 703 14

Abstract:

Systems and methods of performing co-simulation of a partitioned circuit design using multiple programmable logic devices (PLDs) coupled together to form a boundary scan chain. A host computer is coupled to the scan chain via a programming cable. Resident on the host computer are run-time co-simulation blocks corresponding to blocks from the circuit design, where each block is designated to run on one of the PLDs in the scan chain; a programming cable device driver interfacing with the programming cable; and a proxy component. The proxy component is coupled to all of the run-time co-simulation blocks and the programming cable device driver. Each co-simulation block includes a unique pattern identifier, which is also present in the associated PLD. Using this pattern identifier, data and commands targeted to a specific PLD can be extracted from the scan chain, while ignoring data and commands targeted to other PLDs in the scan chain.

US Patent:

7852109, Dec 14, 2010

Filed:

Dec 15, 2008

Appl. No.:

12/335466

Inventors:

Chi Bun Chan - San Jose CA, US
Jingzhao Ou - Sunnyvale CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 19/00

US Classification:

326 16, 326 47, 326 93

Abstract:

A method and apparatus involves operating a circuit having a test circuit interrupt input terminal (INTERRUPT), having a test circuit clock output terminal (DUT_CLK), and having first and second operational modes. In the first operational mode the circuit supplies a test circuit clock signal to the test circuit clock output terminal. The circuit responds to receipt of an occurrence of a test circuit interrupt at the test circuit interrupt input terminal by then operating in the second operational mode. In the second operational mode the circuit refrains from supplying the test circuit clock signal to the test circuit clock output terminal.

US Patent:

7930162, Apr 19, 2011

Filed:

May 5, 2008

Appl. No.:

12/115340

Inventors:

Chi Bun Chan - San Jose CA, US
Shay Ping Seng - San Jose CA, US
Jingzhao Ou - Sunnyvale CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

703 14, 714724

Abstract:

An integrated circuit configured for hardware co-simulation can include a command processor, a replay buffer storing a command template, wherein the command template specifies an incomplete command, and a command first-in-first out (FIFO) memory storing complementary data for completion of the command template. The integrated circuit further can include a multiplexer coupled to the command processor, the replay buffer, and the command FIFO. The multiplexer, under control of the command processor, can selectively provide data from the replay buffer or the command FIFO to the command processor. The command processor, responsive to a replay command read during a hardware co-simulation session, can enter a replay mode, obtain the command template from the replay buffer, obtain the complementary data from the FIFO memory according to a symbol read from the command template, and form a complete command by joining the command template with the complementary data.