Chi Shih Chang

US Patent:

6353182, Mar 5, 2002

Filed:

Mar 30, 1998

Appl. No.:

09/050765

Inventors:

Chi Shih Chang - Austin TX
William T. Chen - Endicott NY
Ajit Trivedi - Endicott NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2328

US Classification:

174 522, 174 523, 174 524, 174255, 174260, 257632, 257678, 257701, 257737, 257738, 361748, 361767

Abstract:

The present invention describes a method and apparatus for packaging a flip chip by matching the z-direction CTE of the IC solder joint with the z-direction CTE of the encapsulant. Consideration of the z-direction CTEs is important when determining the volumetric CTE of the encapsulant. This invention first requires a determination of the z-direction CTE of the IC solder joint and a determination of the z-direction CTE of the encapsulant. The invention next matches the z-direction CTE of the IC solder joint to the z-direction CTE of the encapsulant. The matching of the two z-direction CTEs reduces the z-direction tensile or compression stresses on the IC solder joint and the encapsulant.

US Patent:

6829149, Dec 7, 2004

Filed:

Aug 18, 1997

Appl. No.:

08/912429

Inventors:

Chi Shih Chang - Austin TX
William T. Chen - Endicott NY
Ajit Trivedi - Endicott NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H05K 712

US Classification:

361771, 361704, 361707, 361712, 361714

Abstract:

The present invention discloses techniques that improve the reliability of a flip packages that uses underfill encapsulation. One embodiment of the present invention describes a method and apparatus of packaging a flip chip by relocating the neutral plane of the package substrate away from its mid-plane. Another embodiment of the present invention describes a method and apparatus of arranging the layers of a laminate for use in PBGA packaging that arranges the layers of the laminate according to the stiffness of each layer. Another embodiment of the present invention describes a method and apparatus of packaging a flip chip that uses one or more redundant interconnections at the bottom of the package substrate where the redundant interconnections are within the shadow of the IC chip.

US Patent:

7227268, Jun 5, 2007

Filed:

Oct 29, 2004

Appl. No.:

10/977263

Inventors:

Chi Shih Chang - Austin TX, US
William T. Chen - Endicott NY, US
Ajit Trivedi - Endicott NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 23/48
H01L 23/52
H01L 29/40

US Classification:

257786, 257738, 257778, 257E2302, 257E23021, 257E23023, 257E23069, 438108, 438109

Abstract:

The present invention discloses techniques that improve the reliability of a flip packages that uses underfill encapsulation. One embodiment of the present invention describes a method and apparatus of packaging a flip chip by relocating the neutral plane of the package substrate away from its mid-plane. Another embodiment of the present invention describes a method and apparatus of arranging the layers of a laminate for use in PBGA packaging that arranges the layers of the laminate according to the stiffness of each layer. Another embodiment of the present invention describes a method and apparatus of packaging a flip chip that uses one or more redundant interconnections at the bottom of the package substrate where the redundant interconnections are within the shadow of the IC chip.

US Patent:

7374811, May 20, 2008

Filed:

Apr 5, 2006

Appl. No.:

11/399711

Inventors:

Chi Shih Chang - Austin TX, US
Bahadir Tunaboylu - Chandler AZ, US

Assignee:

SV Probe Pte Ltd. - Singapore

International Classification:

B32B 3/00
H01K 1/03
H05K 1/11

US Classification:

428209, 174255, 174262, 174264, 361803

Abstract:

A method for manufacturing a ceramic device is provided. The ceramic device comprises a ceramic layer. A polyimide layer is on the ceramic layer. The polyimide layer has disposed therein a plurality of copper vias. Each copper via is in physical contact with the ceramic layer. A plurality of pads are formed on the polyimide layer. Each of the plurality of pads is in physical contact with a copper via of the plurality of copper vias. In this way, the pads are supported by a continuous copper arrangement, thereby providing greater support for the probe pads than if the probe pads were supported by the polyimide layer, as the mechanical strength of polyimide layer is lower than the mechanical strength of copper.

US Patent:

61883050, Feb 13, 2001

Filed:

Dec 8, 1995

Appl. No.:

8/569529

Inventors:

Chi Shih Chang - Austin TX
Michael Joseph Johnson - Raleigh NC
Craig Neal Johnston - Concord NH
John Matthew Lauffer - Waverly NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01K 4106

US Classification:

336200

Abstract:

A transformer comprises a printed circuit board having elongated conductors printed thereon, a ferrite core having a bottom mounted onto the printed circuit board and a flex circuit. The flex circuit comprises a dielectric sheet and elongated conductors printed on both faces of the sheet. The flex circuit is contoured around a top and sides of the core. The conductors of the flex circuit are surface bonded to respective conductors of the printed circuit board to form a series of primary windings and a series of secondary windings around the core. Provision of the upper portions of the windings by means of the flex circuit is economical because it does not require handling of discrete conductor portions.

US Patent:

55196330, May 21, 1996

Filed:

Mar 8, 1993

Appl. No.:

8/028098

Inventors:

Chi S. Chang - Endicott NY
Subahu D. Desai - Vestal NY
Debra A. Gernhart - Johnson City NY
Phillip A. Hartley - Vestal NY
Robert J. Haskins - Endwell NY
Keith K. T. Ho - Endicott NY
Robert A. Martone - Endicott NY
Roy T. Mulcahy - Vestal NY
Louis J. Shaffer - Endicott NY
Robert D. Schoening - Endicott NY
Scott A. Versprille - Vestal NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1750

US Classification:

364491

Abstract:

Disclosed is a design tool and a method of fabricating a multi-layer printed circuit board. The method utilizes the design tool. The knowledge base means has both (1) printed circuit board cross sectional geometric parameter to transmission line parameter data and (2) "IF. . . THEN. . . " production rules for lamination, registration, circuitization, testability, test tools, and test procedures. These tools relate to manufacturability, cost, test development, second level packaging and printed circuit board. The printed circuit board begins with the user entering the printed circuit board design parameters and performance parameters into the input/output interface. Next, the knowledge base production rules are applied to the printed circuit board design and performance parameters to generate a set of cross section designs meeting the user specified parameters. The printed circuit board is then built up in accordance with one of the generated cross section designs.

US Patent:

60001305, Dec 14, 1999

Filed:

Apr 20, 1998

Appl. No.:

9/062816

Inventors:

Chi Shih Chang - Austin TX
Frank Daniel Egitto - Binghamton NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01K 310

US Classification:

29852

Abstract:

A self-supporting redistribution structure for directly mounting a semi-conductor chip to a multilayer electronic substrate is separately fabricated and then laminated to the multilayer substrate. The redistribution structure comprises a dielectric layer having plated vias communicating between its two major surfaces, redistribution lines and input/output pads on its upper major surface and joining patterns on its lower margin surface for electrical connection with the multilayer substrate. The metal plating in the plated vias of the redistribution device connects respective input/output pads on the upper surface of the redistribution structures with the joining patterns on its lower major surface. Input/output pads define an even (planar) topography with the redistribution lines to facilitate flip chip joining.

US Patent:

59593482, Sep 28, 1999

Filed:

Aug 18, 1997

Appl. No.:

8/912271

Inventors:

Chi Shih Chang - Austin TX
William T. Chen - Endicott NY
Ajit Trivedi - Endicott NY

Assignee:

International Business Machines Corporation - Armonk NJ
Sematech, Inc. - Austin TX

International Classification:

H01L 25053
H01L 2312
H01L 2314

US Classification:

257700

Abstract:

The present invention discloses techniques that improve the reliability of a flip packages that uses underfill encapsulation. One embodiment of the present invention describes a method and apparatus of packaging a flip chip by relocating the neutral plane of the package substrate away from its mid-plane. Another embodiment of the present invention describes a method and apparatus of arranging the layers of a laminate for use in PBGA packaging that arranges the layers of the laminate according to the stiffness of each layer. Another embodiment of the present invention describes a method and apparatus of packaging a flip chip that uses one or more redundant interconnections at the bottom of the package substrate where the redundant interconnections are within the shadow of the IC chip.