Chi Way Chang

US Patent:

42491932, Feb 3, 1981

Filed:

May 25, 1978

Appl. No.:

5/909605

Inventors:

John Balyoz - Hopewell Junction NY
Chi S. Chang - Wappingers Falls NY
Barry C. Fox - Poughkeepsie NY
John A. Palmieri - Wappingers Falls NY
Majid Ghafghaichi - Poughkeepsie NY
Teh-Sen Jen - Fishkill NY
Donald B. Mooney - Poughkeepsie NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2702

US Classification:

357 40

Abstract:

Disclosed is an improved masterslice design technique including structure, wiring, and method of fabricating, to provide improved Large Scale Integrated Devices. In accordance with the improved masterslice technique a plurality of semiconductor chips are provided wherein essentially the entire semiconductor surface area of each chip is utilized to provide cells selectable to be personalized (wired). None of the semiconductor surface area is dedicated for wiring channels. The individual cell area and cell configuration is optimally arrived at to facilitate wiring the maximum number, if not all of the cells contained on each chip, whereby circuit density is materially improved and a wide variety LSI device part numbers may be readily fabricated.

US Patent:

T162018, Mar 4, 1986

Filed:

Jan 13, 1983

Appl. No.:

6/457786

Inventors:

John Balyoz - Hopewell Junction NY
Chi S. Chang - Wappingers Falls NY
Barry C. Fox - Poughkeepsie NY
John A. Palmieri - Wappingers Falls NY
Majid Ghafghaichi - Poughkeepsie NY
Teh-Sen Jen - Fishkill NY
Donald B. Mooney - Poughkeepsie NY

International Classification:

H01L 2188

US Classification:

29577C

Abstract:

A method for forming an improved integrated circuit chip structure having a surface from which regions of different conductivity type are arranged in a plurality of electrically isolated macro circuits, each macro circuit including interconnected components, a first X pattern of equally spaced parallel conductors overlying and electrically insulated from said chip structure surface, said first X pattern of conductors being selectively connected to at least certain ones of said plurality of macro circuits, a second Y pattern of equally spaced parallel conductors overlying and electrically insulated from said first pattern of parallel conductors, said second Y pattern of conductors being selectively connected to at least selected certain ones of said first pattern of electrical conductors, said spacing one from another of said first X pattern of conductors being equal to said spacing one from another of said second Y pattern of conductors, said first pattern of conductors being orthogonal of said second pattern of conductors, and each of said connections occurring exclusively at points in space corresponding to X-Y intersections of an X-Y coordinate system, where said X-Y coordinate system geometrically corresponds identically to said X-Y pattern of conductors.

US Patent:

42951496, Oct 13, 1981

Filed:

Dec 29, 1978

Appl. No.:

5/974576

Inventors:

John Balyoz - Hopewell Junction NY
Chi S. Chang - Wappingers Falls NY
Barry C. Fox - Poughkeepsie NY
John A. Palmieri - Wappingers Falls NY
Majid Ghafghaichi - Poughkeepsie NY
Teh-Sen Jen - Fishkill NY
Donald B. Mooney - Poughkeepsie NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2710

US Classification:

357 45

Abstract:

Disclosed are improved LSI semiconductor design structures termed "Master Image Chip Organization Techniques". Utilizing the technique provides increased density and optimized performance of semiconductor devices, circuits, and part number functions. In accordance with the disclosed Master Image Chip Organization Method the semiconductor chips are optimally structured to facilitate the maximum number of devices and circuits, and to facilitate fabrication of a wide variety of LSI part numbers. Essentially, none of the semiconductor surface is dedicated for signal and power wiring channels. A master image wiring structure is provided which resides over the semiconductor surface and beneath a power surface. In addition, the master image wiring structure provides a means for personalizing power and signal wiring for a multiple power surface structure. The combined master image structure provides a means for optimally allocating semiconductor area for devices, functional units (micro and macro) and signal and power wiring to facilitate improved density and performance.